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[AMDGPU] Use getSignedConstant() where necessary #117328

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Nov 25, 2024
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[AMDGPU] Use getSignedConstant() where necessary #117328

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12 changes: 6 additions & 6 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2330,10 +2330,10 @@ SDValue SelectionDAGLegalize::expandLdexp(SDNode *Node) const {
const APFloat::ExponentType MinExpVal = APFloat::semanticsMinExponent(FltSem);
const int Precision = APFloat::semanticsPrecision(FltSem);

const SDValue MaxExp = DAG.getConstant(MaxExpVal, dl, ExpVT);
const SDValue MinExp = DAG.getConstant(MinExpVal, dl, ExpVT);
const SDValue MaxExp = DAG.getSignedConstant(MaxExpVal, dl, ExpVT);
const SDValue MinExp = DAG.getSignedConstant(MinExpVal, dl, ExpVT);

const SDValue DoubleMaxExp = DAG.getConstant(2 * MaxExpVal, dl, ExpVT);
const SDValue DoubleMaxExp = DAG.getSignedConstant(2 * MaxExpVal, dl, ExpVT);

const APFloat One(FltSem, "1.0");
APFloat ScaleUpK = scalbn(One, MaxExpVal, APFloat::rmNearestTiesToEven);
Expand Down Expand Up @@ -2375,7 +2375,7 @@ SDValue SelectionDAGLegalize::expandLdexp(SDNode *Node) const {
SDValue IncN0 = DAG.getNode(ISD::ADD, dl, ExpVT, N, Increment0, NUW_NSW);

SDValue ClampMinVal =
DAG.getConstant(3 * MinExpVal + 2 * Precision, dl, ExpVT);
DAG.getSignedConstant(3 * MinExpVal + 2 * Precision, dl, ExpVT);
SDValue ClampN_Small = DAG.getNode(ISD::SMAX, dl, ExpVT, N, ClampMinVal);
SDValue IncN1 =
DAG.getNode(ISD::ADD, dl, ExpVT, ClampN_Small, Increment1, NSW);
Expand All @@ -2385,8 +2385,8 @@ SDValue SelectionDAGLegalize::expandLdexp(SDNode *Node) const {
SDValue ScaleDown1 = DAG.getNode(ISD::FMUL, dl, VT, ScaleDown0, ScaleDownVal);

SDValue ScaleDownTwice = DAG.getSetCC(
dl, SetCCVT, N, DAG.getConstant(2 * MinExpVal + Precision, dl, ExpVT),
ISD::SETULT);
dl, SetCCVT, N,
DAG.getSignedConstant(2 * MinExpVal + Precision, dl, ExpVT), ISD::SETULT);

SDValue SelectN_Small =
DAG.getNode(ISD::SELECT, dl, ExpVT, ScaleDownTwice, IncN1, IncN0);
Expand Down
15 changes: 8 additions & 7 deletions llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
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Expand Up @@ -408,7 +408,8 @@ SDNode *AMDGPUDAGToDAGISel::glueCopyToM0LDSInit(SDNode *N) const {
unsigned AS = cast<MemSDNode>(N)->getAddressSpace();
if (AS == AMDGPUAS::LOCAL_ADDRESS) {
if (Subtarget->ldsRequiresM0Init())
return glueCopyToM0(N, CurDAG->getTargetConstant(-1, SDLoc(N), MVT::i32));
return glueCopyToM0(
N, CurDAG->getSignedTargetConstant(-1, SDLoc(N), MVT::i32));
} else if (AS == AMDGPUAS::REGION_ADDRESS) {
MachineFunction &MF = CurDAG->getMachineFunction();
unsigned Value = MF.getInfo<SIMachineFunctionInfo>()->getGDSSize();
Expand Down Expand Up @@ -1724,7 +1725,7 @@ bool AMDGPUDAGToDAGISel::SelectFlatOffsetImpl(SDNode *N, SDValue Addr,
}

VAddr = Addr;
Offset = CurDAG->getTargetConstant(OffsetVal, SDLoc(), MVT::i32);
Offset = CurDAG->getSignedTargetConstant(OffsetVal, SDLoc(), MVT::i32);
return true;
}

Expand Down Expand Up @@ -1832,7 +1833,7 @@ bool AMDGPUDAGToDAGISel::SelectGlobalSAddr(SDNode *N,
}

if (SAddr) {
Offset = CurDAG->getTargetConstant(ImmOffset, SDLoc(), MVT::i32);
Offset = CurDAG->getSignedTargetConstant(ImmOffset, SDLoc(), MVT::i32);
return true;
}
}
Expand All @@ -1848,7 +1849,7 @@ bool AMDGPUDAGToDAGISel::SelectGlobalSAddr(SDNode *N,
CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, SDLoc(Addr), MVT::i32,
CurDAG->getTargetConstant(0, SDLoc(), MVT::i32));
VOffset = SDValue(VMov, 0);
Offset = CurDAG->getTargetConstant(ImmOffset, SDLoc(), MVT::i32);
Offset = CurDAG->getSignedTargetConstant(ImmOffset, SDLoc(), MVT::i32);
return true;
}

Expand Down Expand Up @@ -1903,13 +1904,13 @@ bool AMDGPUDAGToDAGISel::SelectScratchSAddr(SDNode *Parent, SDValue Addr,
SDValue AddOffset =
SAddr.getOpcode() == ISD::TargetFrameIndex
? getMaterializedScalarImm32(Lo_32(RemainderOffset), DL)
: CurDAG->getTargetConstant(RemainderOffset, DL, MVT::i32);
: CurDAG->getSignedTargetConstant(RemainderOffset, DL, MVT::i32);
SAddr = SDValue(CurDAG->getMachineNode(AMDGPU::S_ADD_I32, DL, MVT::i32,
SAddr, AddOffset),
0);
}

Offset = CurDAG->getTargetConstant(COffsetVal, DL, MVT::i32);
Offset = CurDAG->getSignedTargetConstant(COffsetVal, DL, MVT::i32);

return true;
}
Expand Down Expand Up @@ -2058,7 +2059,7 @@ bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
std::optional<int64_t> EncodedOffset = AMDGPU::getSMRDEncodedOffset(
*Subtarget, ByteOffset, IsBuffer, HasSOffset);
if (EncodedOffset && Offset && !Imm32Only) {
*Offset = CurDAG->getTargetConstant(*EncodedOffset, SL, MVT::i32);
*Offset = CurDAG->getSignedTargetConstant(*EncodedOffset, SL, MVT::i32);
return true;
}

Expand Down
8 changes: 6 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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Expand Up @@ -2333,7 +2333,7 @@ SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
SDValue RHS = Op.getOperand(1);

SDValue Zero = DAG.getConstant(0, DL, VT);
SDValue NegOne = DAG.getConstant(-1, DL, VT);
SDValue NegOne = DAG.getAllOnesConstant(DL, VT);

if (VT == MVT::i32) {
if (SDValue Res = LowerDIVREM24(Op, DAG, true))
Expand Down Expand Up @@ -3794,7 +3794,11 @@ static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset,
if (Width + Offset < 32) {
uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
return DAG.getConstant(Result, DL, MVT::i32);
if constexpr (std::is_signed_v<IntTy>) {
return DAG.getSignedConstant(Result, DL, MVT::i32);
} else {
return DAG.getConstant(Result, DL, MVT::i32);
}
}

return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
Expand Down
14 changes: 7 additions & 7 deletions llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
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Expand Up @@ -919,7 +919,7 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
HWTrue = DAG.getConstantFP(1.0f, DL, CompareVT);
HWFalse = DAG.getConstantFP(0.0f, DL, CompareVT);
} else if (CompareVT == MVT::i32) {
HWTrue = DAG.getConstant(-1, DL, CompareVT);
HWTrue = DAG.getAllOnesConstant(DL, CompareVT);
HWFalse = DAG.getConstant(0, DL, CompareVT);
}
else {
Expand Down Expand Up @@ -949,7 +949,7 @@ SDValue R600TargetLowering::lowerADDRSPACECAST(SDValue Op,
unsigned DestAS = ASC->getDestAddressSpace();

if (isNullConstant(Op.getOperand(0)) && SrcAS == AMDGPUAS::FLAT_ADDRESS)
return DAG.getConstant(TM.getNullPointerValue(DestAS), SL, VT);
return DAG.getSignedConstant(TM.getNullPointerValue(DestAS), SL, VT);

return Op;
}
Expand Down Expand Up @@ -1750,11 +1750,11 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
}

return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0),
SelectCC.getOperand(0), // LHS
SelectCC.getOperand(1), // RHS
DAG.getConstant(-1, DL, MVT::i32), // True
DAG.getConstant(0, DL, MVT::i32), // False
SelectCC.getOperand(4)); // CC
SelectCC.getOperand(0), // LHS
SelectCC.getOperand(1), // RHS
DAG.getAllOnesConstant(DL, MVT::i32), // True
DAG.getConstant(0, DL, MVT::i32), // False
SelectCC.getOperand(4)); // CC
}

// insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
Expand Down
30 changes: 16 additions & 14 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Expand Up @@ -4019,10 +4019,11 @@ SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(SDValue Op,
Align StackAlign = TFL->getStackAlign();
Tmp1 = DAG.getNode(Opc, dl, VT, SP, ScaledSize); // Value
if (Alignment && *Alignment > StackAlign) {
Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
DAG.getConstant(-(uint64_t)Alignment->value()
<< Subtarget->getWavefrontSizeLog2(),
dl, VT));
Tmp1 = DAG.getNode(
ISD::AND, dl, VT, Tmp1,
DAG.getSignedConstant(-(uint64_t)Alignment->value()
<< Subtarget->getWavefrontSizeLog2(),
dl, VT));
}

Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
Expand Down Expand Up @@ -6771,10 +6772,10 @@ SDValue SITargetLowering::lowerFLDEXP(SDValue Op, SelectionDAG &DAG) const {
// TODO: This should be a generic narrowing legalization, and can easily be
// for GlobalISel.

SDValue MinExp = DAG.getConstant(minIntN(16), DL, ExpVT);
SDValue MinExp = DAG.getSignedConstant(minIntN(16), DL, ExpVT);
SDValue ClampMin = DAG.getNode(ISD::SMAX, DL, ExpVT, Exp, MinExp);

SDValue MaxExp = DAG.getConstant(maxIntN(16), DL, ExpVT);
SDValue MaxExp = DAG.getSignedConstant(maxIntN(16), DL, ExpVT);
SDValue Clamp = DAG.getNode(ISD::SMIN, DL, ExpVT, ClampMin, MaxExp);

SDValue TruncExp = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Clamp);
Expand Down Expand Up @@ -7542,11 +7543,11 @@ SDValue SITargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,

SDValue Vec0 = SVN->getOperand(VecIdx0);
SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec0,
DAG.getConstant(EltIdx0, SL, MVT::i32));
DAG.getSignedConstant(EltIdx0, SL, MVT::i32));

SDValue Vec1 = SVN->getOperand(VecIdx1);
SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Vec1,
DAG.getConstant(EltIdx1, SL, MVT::i32));
DAG.getSignedConstant(EltIdx1, SL, MVT::i32));
Pieces.push_back(DAG.getBuildVector(PackVT, SL, {Elt0, Elt1}));
}
}
Expand Down Expand Up @@ -9618,7 +9619,7 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
// On GFX12 lower s_barrier into s_barrier_signal_imm and s_barrier_wait
if (ST.hasSplitBarriers()) {
SDValue K =
DAG.getTargetConstant(AMDGPU::Barrier::WORKGROUP, DL, MVT::i32);
DAG.getSignedTargetConstant(AMDGPU::Barrier::WORKGROUP, DL, MVT::i32);
SDValue BarSignal =
SDValue(DAG.getMachineNode(AMDGPU::S_BARRIER_SIGNAL_IMM, DL,
MVT::Other, K, Op.getOperand(0)),
Expand Down Expand Up @@ -11173,8 +11174,9 @@ SDValue SITargetLowering::lowerFSQRTF32(SDValue Op, SelectionDAG &DAG) const {
SqrtS = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, SqrtID, SqrtX, Flags);

SDValue SqrtSAsInt = DAG.getNode(ISD::BITCAST, DL, MVT::i32, SqrtS);
SDValue SqrtSNextDownInt = DAG.getNode(ISD::ADD, DL, MVT::i32, SqrtSAsInt,
DAG.getConstant(-1, DL, MVT::i32));
SDValue SqrtSNextDownInt =
DAG.getNode(ISD::ADD, DL, MVT::i32, SqrtSAsInt,
DAG.getAllOnesConstant(DL, MVT::i32));
SDValue SqrtSNextDown = DAG.getNode(ISD::BITCAST, DL, VT, SqrtSNextDownInt);

SDValue NegSqrtSNextDown =
Expand Down Expand Up @@ -11296,7 +11298,7 @@ SDValue SITargetLowering::lowerFSQRTF64(SDValue Op, SelectionDAG &DAG) const {

SDValue SqrtRet = DAG.getNode(ISD::FMA, DL, MVT::f64, SqrtD1, SqrtH1, SqrtS2);

SDValue ScaleDownFactor = DAG.getConstant(-128, DL, MVT::i32);
SDValue ScaleDownFactor = DAG.getSignedConstant(-128, DL, MVT::i32);
SDValue ScaleDown =
DAG.getNode(ISD::SELECT, DL, MVT::i32, Scaling, ScaleDownFactor, ZeroInt);
SqrtRet = DAG.getNode(ISD::FLDEXP, DL, MVT::f64, SqrtRet, ScaleDown, Flags);
Expand Down Expand Up @@ -14689,7 +14691,7 @@ SDValue SITargetLowering::performSetCCCombine(SDNode *N,
(CRHS->isZero() &&
(CC == ISD::SETEQ || CC == ISD::SETGE || CC == ISD::SETULE)))
return DAG.getNode(ISD::XOR, SL, MVT::i1, LHS.getOperand(0),
DAG.getConstant(-1, SL, MVT::i1));
DAG.getAllOnesConstant(SL, MVT::i1));
if ((CRHS->isAllOnes() &&
(CC == ISD::SETEQ || CC == ISD::SETLE || CC == ISD::SETUGE)) ||
(CRHS->isZero() &&
Expand All @@ -14715,7 +14717,7 @@ SDValue SITargetLowering::performSetCCCombine(SDNode *N,
if ((CF == CRHSVal && CC == ISD::SETEQ) ||
(CT == CRHSVal && CC == ISD::SETNE))
return DAG.getNode(ISD::XOR, SL, MVT::i1, LHS.getOperand(0),
DAG.getConstant(-1, SL, MVT::i1));
DAG.getAllOnesConstant(SL, MVT::i1));
if ((CF == CRHSVal && CC == ISD::SETNE) ||
(CT == CRHSVal && CC == ISD::SETEQ))
return LHS.getOperand(0);
Expand Down
14 changes: 8 additions & 6 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
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Expand Up @@ -812,27 +812,29 @@ def as_i8imm : SDNodeXForm<imm, [{
}]>;

def as_i8timm : SDNodeXForm<timm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
return CurDAG->getSignedTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
}]>;

def as_i16imm : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
return CurDAG->getSignedTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
}]>;

def as_i16timm : SDNodeXForm<timm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
// Explicit cast, as this is used with both signed and unsigned immediates.
return CurDAG->getSignedTargetConstant(int16_t(N->getSExtValue()), SDLoc(N),
MVT::i16);
}]>;

def as_i32imm: SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
return CurDAG->getSignedTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
}]>;

def as_i32timm: SDNodeXForm<timm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
return CurDAG->getSignedTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
}]>;

def as_i64imm: SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
return CurDAG->getSignedTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
}]>;

def cond_as_i32imm: SDNodeXForm<cond, [{
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIInstructions.td
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Expand Up @@ -3727,7 +3727,7 @@ def FPPow2ToExponentXForm : SDNodeXForm<fpimm, [{
const auto &APF = N->getValueAPF();
int Log2 = APF.getExactLog2Abs();
assert(Log2 != INT_MIN);
return CurDAG->getTargetConstant(Log2, SDLoc(N), MVT::i32);
return CurDAG->getSignedTargetConstant(Log2, SDLoc(N), MVT::i32);
}]>;

// Check if a floating point value is a power of 2 floating-point
Expand Down
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