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release/19.x: [RISCV] Add hasPostISelHook to sf.vfnrclip pseudo instructions. (#114274) #117948

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Merged
merged 2 commits into from
Jan 13, 2025
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release/19.x: [RISCV] Add hasPostISelHook to sf.vfnrclip pseudo instructions. (#114274) #117948

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a0dfd3d
[RISCV] Add missing hasPostISelHook = 1 to vector pseudos that might …
topperc Oct 30, 2024
d749beb
[RISCV] Add hasPostISelHook to sf.vfnrclip pseudo instructions. (#114…
topperc Oct 30, 2024
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7 changes: 7 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Expand Up @@ -2536,6 +2536,13 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
}
}

if (int Idx = RISCVII::getFRMOpNum(Desc);
Idx >= 0 && MI.getOperand(Idx).getImm() == RISCVFPRndMode::DYN &&
!MI.readsRegister(RISCV::FRM, /*TRI=*/nullptr)) {
ErrInfo = "dynamic rounding mode should read FRM";
return false;
}

return true;
}

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17 changes: 8 additions & 9 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Expand Up @@ -6471,7 +6471,7 @@ defm PseudoVFRDIV : VPseudoVFRDIV_VF_RM;
//===----------------------------------------------------------------------===//
// 13.5. Vector Widening Floating-Point Multiply
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in {
let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in {
defm PseudoVFWMUL : VPseudoVWMUL_VV_VF_RM;
}

Expand Down Expand Up @@ -6504,7 +6504,7 @@ defm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM;
//===----------------------------------------------------------------------===//
// 13.8. Vector Floating-Point Square-Root Instruction
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in
let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in
defm PseudoVFSQRT : VPseudoVSQR_V_RM;

//===----------------------------------------------------------------------===//
Expand All @@ -6516,7 +6516,7 @@ defm PseudoVFRSQRT7 : VPseudoVRCP_V;
//===----------------------------------------------------------------------===//
// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in
let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in
defm PseudoVFREC7 : VPseudoVRCP_V_RM;

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -6627,9 +6627,10 @@ defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W_RM;
defm PseudoVFNCVT_RM_F_XU : VPseudoVNCVTF_RM_W;
defm PseudoVFNCVT_RM_F_X : VPseudoVNCVTF_RM_W;

let hasSideEffects = 0, hasPostISelHook = 1 in
let hasSideEffects = 0, hasPostISelHook = 1 in {
defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W_RM;
defm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM;
}

defm PseudoVFNCVT_ROD_F_F : VPseudoVNCVTD_W;
} // mayRaiseFPException = true
Expand Down Expand Up @@ -6665,8 +6666,7 @@ let Predicates = [HasVInstructionsAnyF] in {
//===----------------------------------------------------------------------===//
// 14.3. Vector Single-Width Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true,
hasSideEffects = 0 in {
let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in {
defm PseudoVFREDOSUM : VPseudoVFREDO_VS_RM;
defm PseudoVFREDUSUM : VPseudoVFRED_VS_RM;
}
Expand All @@ -6678,9 +6678,8 @@ defm PseudoVFREDMAX : VPseudoVFREDMINMAX_VS;
//===----------------------------------------------------------------------===//
// 14.4. Vector Widening Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
let IsRVVWideningReduction = 1,
hasSideEffects = 0,
mayRaiseFPException = true in {
let IsRVVWideningReduction = 1, hasSideEffects = 0, mayRaiseFPException = true,
hasPostISelHook = 1 in {
defm PseudoVFWREDUSUM : VPseudoVFWRED_VS_RM;
defm PseudoVFWREDOSUM : VPseudoVFWREDO_VS_RM;
}
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5 changes: 3 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
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Expand Up @@ -217,7 +217,8 @@ let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvfwmaccqqq" in
def VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">;
}

let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvfnrclipxfqf" in {
let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvfnrclipxfqf",
Uses = [FRM] in {
def VFNRCLIP_XU_F_QF : CustomSiFiveVFNRCLIP<0b100010, OPFVF, "sf.vfnrclip.xu.f.qf">;
def VFNRCLIP_X_F_QF : CustomSiFiveVFNRCLIP<0b100011, OPFVF, "sf.vfnrclip.x.f.qf">;
}
Expand Down Expand Up @@ -399,7 +400,7 @@ multiclass VPseudoSiFiveVFWMACC<string Constraint = ""> {

multiclass VPseudoSiFiveVFNRCLIP<string Constraint = "@earlyclobber $rd"> {
foreach i = 0-4 in
let hasSideEffects = 0 in
let hasSideEffects = 0, hasPostISelHook = 1 in
defm "Pseudo" # NAME : VPseudoBinaryRoundingMode<MxListW[i].vrclass,
MxListVF4[i].vrclass,
FPR32, MxListW[i],
Expand Down
4 changes: 1 addition & 3 deletions llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll
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Expand Up @@ -13,18 +13,16 @@ declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.iXLen(
define <vscale x 1 x i8> @intrinsic_sf_vfnrclip_x_f_qf_nxv1i8_nxv1f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_nxv1i8_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: sf.vfnrclip.x.f.qf v9, v8, fa0
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.iXLen(
<vscale x 1 x i8> undef,
<vscale x 1 x float> %0,
float %1,
iXLen 0, iXLen %2)
iXLen 7, iXLen %2)

ret <vscale x 1 x i8> %a
}
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4 changes: 1 addition & 3 deletions llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll
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Expand Up @@ -13,18 +13,16 @@ declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.iXLen(
define <vscale x 1 x i8> @intrinsic_sf_vfnrclip_xu_f_qf_nxv1i8_nxv1f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv1i8_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fsrmi a1, 0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: sf.vfnrclip.xu.f.qf v9, v8, fa0
; CHECK-NEXT: fsrm a1
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.iXLen(
<vscale x 1 x i8> undef,
<vscale x 1 x float> %0,
float %1,
iXLen 0, iXLen %2)
iXLen 7, iXLen %2)

ret <vscale x 1 x i8> %a
}
Expand Down
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