[RISCV][Xqcicsr] Instructions have Side Effects

[lenary]

Xqcicsr was added in #117169. I missed that hasSideEffects was set to 0, rather than 1 (which all other CSR-modifying instructions have).

This has no effect on the current assembly-only support, but I think is worth fixing before I forget. I accidentally fixed the closing comment in 9300274.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Sam Elliott (lenary)

Changes

Xqcicsr was added in #117169. I missed that hasSideEffects was set to 0, rather than 1 (which all other CSR-modifying instructions have).

This has no effect on the current assembly-only support, but I think is worth fixing before I forget. I accidentally fixed the closing comment in 9300274.

---

Full diff: https://github.com/llvm/llvm-project/pull/118089.diff

1 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+1-1)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 80d83fce038b29..3f53165d5235e6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -50,7 +50,7 @@ class QCIStore_ScaleIdx<bits<4> func4, string opcodestr>
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr" in {
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
   def QC_CSRRWR : RVInstR<0b1000110, 0b000, OPC_SYSTEM, (outs GPR:$rd),
                           (ins GPR:$rs1, GPRNoX0:$rs2), "qc.csrrwr",
                           "$rd, $rs1, $rs2">;

[svs-quic]

LGTM