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5 changes: 4 additions & 1 deletion llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -15495,12 +15495,15 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
unsigned BuildVecNumElts = BuildVect.getNumOperands();
unsigned TruncVecNumElts = VT.getVectorNumElements();
unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts;
unsigned FirstElt =
DAG.getDataLayout().isBigEndian() ? (TruncEltOffset - 1) : 0;
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visitTRUNCATE already has isLE - replace this with:

unsigned FirstElt =isLE ? 0 : (TruncEltOffset - 1);


assert((BuildVecNumElts % TruncVecNumElts) == 0 &&
"Invalid number of elements");

SmallVector<SDValue, 8> Opnds;
for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset)
for (unsigned i = FirstElt, e = BuildVecNumElts; i < e;
i += TruncEltOffset)
Opnds.push_back(BuildVect.getOperand(i));

return DAG.getBuildVector(VT, DL, Opnds);
Expand Down
31 changes: 31 additions & 0 deletions llvm/test/CodeGen/ARM/big-endian-vector-trunc.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,31 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=armebv7-unknown-none-eabihf -mattr=+neon < %s | FileCheck %s

define i32 @test(i64 %arg1) {
; CHECK-LABEL: test:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: subs r1, r1, #1
; CHECK-NEXT: mov r2, #0
; CHECK-NEXT: sbcs r0, r0, #0
; CHECK-NEXT: vldr s0, .LCPI0_0
; CHECK-NEXT: movwhs r2, #1
; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: mvnne r2, #0
; CHECK-NEXT: vmov s1, r2
; CHECK-NEXT: vmovn.i32 d16, q0
; CHECK-NEXT: vmovn.i16 d16, q8
; CHECK-NEXT: vmov.u8 r0, d16[0]
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI0_0:
; CHECK-NEXT: .long 0xffffffff @ float NaN
entry:
%insert_zero = insertelement <8 x i64> poison, i64 %arg1, i64 0
%splat_zero = shufflevector <8 x i64> %insert_zero, <8 x i64> poison, <8 x i32> zeroinitializer
%cmp_vec = icmp ule <8 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>, %splat_zero
%first_cmp = extractelement <8 x i1> %cmp_vec, i32 0
%ext = zext i1 %first_cmp to i32
ret i32 %ext
}