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[AArch64] Implement FP8 SVE Intrinsics for narrowing conversions #118124
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101
clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
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| Original file line number | Diff line number | Diff line change |
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| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 | ||
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s | ||
| // RUN: %clang_cc1 -x c++ -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CHECK-CXX | ||
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| // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s | ||
| // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -x c++ -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CHECK-CXX | ||
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| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +fp8 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s | ||
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +fp8 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s | ||
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| // REQUIRES: aarch64-registered-target | ||
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| #ifdef __ARM_FEATURE_SME | ||
| #include <arm_sme.h> | ||
| #else | ||
| #include <arm_sve.h> | ||
| #endif | ||
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| #ifdef SVE_OVERLOADED_FORMS | ||
| #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3 | ||
| #else | ||
| #define SVE_ACLE_FUNC(A1,A2,A3) A1##A2##A3 | ||
| #endif | ||
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| #ifdef __ARM_FEATURE_SME | ||
| #define STREAMING __arm_streaming | ||
| #else | ||
| #define STREAMING | ||
| #endif | ||
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| // CHECK-LABEL: define dso_local <vscale x 16 x i8> @test_svcvtn_f8_bf16( | ||
| // CHECK-SAME: <vscale x 8 x bfloat> [[ZN_ZM_COERCE0:%.*]], <vscale x 8 x bfloat> [[ZN_ZM_COERCE1:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(<vscale x 8 x bfloat> [[ZN_ZM_COERCE0]], <vscale x 8 x bfloat> [[ZN_ZM_COERCE1]]) | ||
| // CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] | ||
| // | ||
| // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z19test_svcvtn_f8_bf1614svbfloat16x2_tm( | ||
| // CHECK-CXX-SAME: <vscale x 8 x bfloat> [[ZN_ZM_COERCE0:%.*]], <vscale x 8 x bfloat> [[ZN_ZM_COERCE1:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0:[0-9]+]] { | ||
| // CHECK-CXX-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(<vscale x 8 x bfloat> [[ZN_ZM_COERCE0]], <vscale x 8 x bfloat> [[ZN_ZM_COERCE1]]) | ||
| // CHECK-CXX-NEXT: ret <vscale x 16 x i8> [[TMP0]] | ||
| // | ||
| svmfloat8_t test_svcvtn_f8_bf16(svbfloat16x2_t zn_zm, fpm_t fpm) STREAMING { | ||
| return SVE_ACLE_FUNC(svcvtn_mf8,_bf16_x2,_fpm)(zn_zm, fpm); | ||
| } | ||
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| // CHECK-LABEL: define dso_local <vscale x 16 x i8> @test_svcvtn_f8_f16( | ||
| // CHECK-SAME: <vscale x 8 x half> [[ZN_ZM_COERCE0:%.*]], <vscale x 8 x half> [[ZN_ZM_COERCE1:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8f16(<vscale x 8 x half> [[ZN_ZM_COERCE0]], <vscale x 8 x half> [[ZN_ZM_COERCE1]]) | ||
| // CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] | ||
| // | ||
| // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z18test_svcvtn_f8_f1613svfloat16x2_tm( | ||
| // CHECK-CXX-SAME: <vscale x 8 x half> [[ZN_ZM_COERCE0:%.*]], <vscale x 8 x half> [[ZN_ZM_COERCE1:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-CXX-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8f16(<vscale x 8 x half> [[ZN_ZM_COERCE0]], <vscale x 8 x half> [[ZN_ZM_COERCE1]]) | ||
| // CHECK-CXX-NEXT: ret <vscale x 16 x i8> [[TMP0]] | ||
| // | ||
| svmfloat8_t test_svcvtn_f8_f16(svfloat16x2_t zn_zm, fpm_t fpm) STREAMING { | ||
| return SVE_ACLE_FUNC(svcvtn_mf8,_f16_x2,_fpm)(zn_zm, fpm); | ||
| } | ||
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| // CHECK-LABEL: define dso_local <vscale x 16 x i8> @test_svcvtnb_f8_f32( | ||
| // CHECK-SAME: <vscale x 4 x float> [[ZN_ZM_COERCE0:%.*]], <vscale x 4 x float> [[ZN_ZM_COERCE1:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(<vscale x 4 x float> [[ZN_ZM_COERCE0]], <vscale x 4 x float> [[ZN_ZM_COERCE1]]) | ||
| // CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] | ||
| // | ||
| // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z19test_svcvtnb_f8_f3213svfloat32x2_tm( | ||
| // CHECK-CXX-SAME: <vscale x 4 x float> [[ZN_ZM_COERCE0:%.*]], <vscale x 4 x float> [[ZN_ZM_COERCE1:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-CXX-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(<vscale x 4 x float> [[ZN_ZM_COERCE0]], <vscale x 4 x float> [[ZN_ZM_COERCE1]]) | ||
| // CHECK-CXX-NEXT: ret <vscale x 16 x i8> [[TMP0]] | ||
| // | ||
| svmfloat8_t test_svcvtnb_f8_f32(svfloat32x2_t zn_zm, fpm_t fpm) STREAMING { | ||
| return SVE_ACLE_FUNC(svcvtnb_mf8,_f32_x2,_fpm)(zn_zm, fpm); | ||
| } | ||
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| // CHECK-LABEL: define dso_local <vscale x 16 x i8> @test_svcvtnt_f8_f32( | ||
| // CHECK-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 4 x float> [[ZN_ZM_COERCE0:%.*]], <vscale x 4 x float> [[ZN_ZM_COERCE1:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(<vscale x 16 x i8> [[ZD]], <vscale x 4 x float> [[ZN_ZM_COERCE0]], <vscale x 4 x float> [[ZN_ZM_COERCE1]]) | ||
| // CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] | ||
| // | ||
| // CHECK-CXX-LABEL: define dso_local <vscale x 16 x i8> @_Z19test_svcvtnt_f8_f32u13__SVMfloat8_t13svfloat32x2_tm( | ||
| // CHECK-CXX-SAME: <vscale x 16 x i8> [[ZD:%.*]], <vscale x 4 x float> [[ZN_ZM_COERCE0:%.*]], <vscale x 4 x float> [[ZN_ZM_COERCE1:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] { | ||
| // CHECK-CXX-NEXT: [[ENTRY:.*:]] | ||
| // CHECK-CXX-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPM]]) | ||
| // CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(<vscale x 16 x i8> [[ZD]], <vscale x 4 x float> [[ZN_ZM_COERCE0]], <vscale x 4 x float> [[ZN_ZM_COERCE1]]) | ||
| // CHECK-CXX-NEXT: ret <vscale x 16 x i8> [[TMP0]] | ||
| // | ||
| svmfloat8_t test_svcvtnt_f8_f32(svmfloat8_t zd, svfloat32x2_t zn_zm, fpm_t fpm) STREAMING { | ||
| return SVE_ACLE_FUNC(svcvtnt_mf8,_f32_x2,_fpm)(zd, zn_zm, fpm); | ||
| } | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,49 @@ | ||
| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 | ||
| ; RUN: llc -mattr=+sve2,+fp8 < %s | FileCheck %s | ||
| ; RUN: llc -mattr=+sme2,+fp8 --force-streaming < %s | FileCheck %s | ||
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| target triple = "aarch64-linux" | ||
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| define <vscale x 16 x i8> @cvtn_bf16(<vscale x 8 x bfloat> %s1, <vscale x 8 x bfloat> %s2) { | ||
| ; CHECK-LABEL: cvtn_bf16: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1 | ||
| ; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1 | ||
| ; CHECK-NEXT: bfcvtn z0.b, { z0.h, z1.h } | ||
| ; CHECK-NEXT: ret | ||
| %r = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8bf16(<vscale x 8 x bfloat> %s1, <vscale x 8 x bfloat> %s2) | ||
| ret <vscale x 16 x i8> %r | ||
| } | ||
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| define <vscale x 16 x i8> @cvtn_f16(<vscale x 8 x half> %s1, <vscale x 8 x half> %s2) { | ||
| ; CHECK-LABEL: cvtn_f16: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1 | ||
| ; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1 | ||
| ; CHECK-NEXT: fcvtn z0.b, { z0.h, z1.h } | ||
| ; CHECK-NEXT: ret | ||
| %r = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.nxv8f16(<vscale x 8 x half> %s1, <vscale x 8 x half> %s2) | ||
| ret <vscale x 16 x i8> %r | ||
| } | ||
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| define <vscale x 16 x i8> @cvtnb_f32(<vscale x 4 x float> %s1, <vscale x 4 x float> %s2) { | ||
| ; CHECK-LABEL: cvtnb_f32: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1 | ||
| ; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1 | ||
| ; CHECK-NEXT: fcvtnb z0.b, { z0.s, z1.s } | ||
| ; CHECK-NEXT: ret | ||
| %r = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnb.nxv4f32(<vscale x 4 x float> %s1, <vscale x 4 x float> %s2) | ||
| ret <vscale x 16 x i8> %r | ||
| } | ||
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| define <vscale x 16 x i8> @cvtnt_f32(<vscale x 16 x i8> %d, <vscale x 4 x float> %s1, <vscale x 4 x float> %s2) { | ||
| ; CHECK-LABEL: cvtnt_f32: | ||
| ; CHECK: // %bb.0: | ||
| ; CHECK-NEXT: mov z3.d, z2.d | ||
| ; CHECK-NEXT: mov z2.d, z1.d | ||
| ; CHECK-NEXT: fcvtnt z0.b, { z2.s, z3.s } | ||
| ; CHECK-NEXT: ret | ||
| %r = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtnt.nxv4f32(<vscale x 16 x i8> %d, <vscale x 4 x float> %s1, <vscale x 4 x float> %s2) | ||
| ret <vscale x 16 x i8> %r | ||
| } |
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