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[RISCV] Use LiveIntervals to determine if AVL dominates when coalescing #118285

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Merged
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Dec 2, 2024
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[RISCV] Use LiveIntervals to determine if AVL dominates when coalescing #118285

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[RISCV] Use LiveIntervals to determine if AVL dominates when coalescing
lukel97 Dec 2, 2024
f2b9c4a
Compare VNInfo pointers directly. This seems to be fine and is done e…
lukel97 Dec 2, 2024
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15 changes: 8 additions & 7 deletions llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1619,14 +1619,15 @@ bool RISCVInsertVSETVLI::canMutatePriorConfig(
}

auto &AVL = MI.getOperand(1);
auto &PrevAVL = PrevMI.getOperand(1);

// If the AVL is a register, we need to make sure MI's AVL dominates PrevMI.
// For now just check that PrevMI uses the same virtual register.
if (AVL.isReg() && AVL.getReg() != RISCV::X0 &&
(!MRI->hasOneDef(AVL.getReg()) || !PrevAVL.isReg() ||
PrevAVL.getReg() != AVL.getReg()))
return false;
// If the AVL is a register, we need to make sure its definition is the same
// at PrevMI as it was at MI.
if (AVL.isReg() && AVL.getReg() != RISCV::X0) {
VNInfo *VNI = getVNInfoFromReg(AVL.getReg(), MI, LIS);
VNInfo *PrevVNI = getVNInfoFromReg(AVL.getReg(), PrevMI, LIS);
if (!VNI || !PrevVNI || VNI->id != PrevVNI->id)
return false;
}
}

assert(PrevMI.getOperand(2).isImm() && MI.getOperand(2).isImm());
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13 changes: 6 additions & 7 deletions llvm/test/CodeGen/RISCV/rvv/compressstore.ll
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Expand Up @@ -652,15 +652,14 @@ define void @test_compresstore_v64i32(ptr %p, <64 x i1> %mask, <64 x i32> %data)
; RV64-NEXT: vse32.v v24, (a0)
; RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vi v8, v0, 4
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV64-NEXT: vmv.x.s a2, v0
; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV64-NEXT: vmv.x.s a1, v0
; RV64-NEXT: vcompress.vm v24, v16, v8
; RV64-NEXT: vcpop.m a1, v8
; RV64-NEXT: cpopw a2, a2
; RV64-NEXT: slli a2, a2, 2
; RV64-NEXT: add a0, a0, a2
; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV64-NEXT: vcpop.m a2, v8
; RV64-NEXT: cpopw a1, a1
; RV64-NEXT: slli a1, a1, 2
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV64-NEXT: vse32.v v24, (a0)
; RV64-NEXT: ret
;
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