Skip to content

[RISCV] Intrinsic Support for XCVsimd #118557

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 6 commits into
base: main
Choose a base branch
from
Open

[RISCV] Intrinsic Support for XCVsimd #118557

Show file tree
Hide file tree
Changes from 5 commits
Commits
Show all changes
6 commits
Select commit Hold shift + click to select a range
9beb1c6
[RISCV] Intrinsic Support for XCVsimd
realqhc Nov 27, 2024
29b9988
fix formatter error, use DefaultAttrsIntrinsic instead of Intrinsic
realqhc Dec 11, 2024
b6e80d4
move CV_SHUFFLE_SCI_B expansion from RISCVExpandPseudoInsts.cpp to RI…
realqhc Dec 20, 2024
d46bea2
format
realqhc Dec 20, 2024
025a4f9
use SignExtend64<6> instead of APInt
realqhc Dec 27, 2024
2e2192f
remove unused class, fix indentation and align class name
realqhc Feb 28, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
124 changes: 124 additions & 0 deletions llvm/include/llvm/IR/IntrinsicsRISCVXCV.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,70 @@ class ScalarCoreVMacGprGprGprImmIntrinsic
: Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, IntrWillReturn, IntrSpeculatable, ImmArg<ArgIndex<3>>]>;

class ScalarCoreVSimdGprIntrinsic
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty],
[IntrNoMem, IntrSpeculatable]>;

class ScalarCoreVSimdGprGprIntrinsic
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, IntrSpeculatable]>;

class ScalarCoreVSimdGprImmIntrinsic
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<1>>]>;

class ScalarCoreVSimdGprGprGprIntrinsic
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, IntrSpeculatable]>;

class ScalarCoreVSimdGprGprImmIntrinsic
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<2>>]>;

class ScalarCoreVSimdGprGprGprImmIntrinsic
: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
[IntrNoMem, IntrSpeculatable, ImmArg<ArgIndex<3>>]>;

multiclass ScalarCoreVSimdGprIntrinsicHB {
def int_riscv_cv_simd_ # NAME # _h : ScalarCoreVSimdGprIntrinsic;
def int_riscv_cv_simd_ # NAME # _b : ScalarCoreVSimdGprIntrinsic;
}

multiclass ScalarCoreVSimdGprGprIntrinsicHB {
def int_riscv_cv_simd_ # NAME # _h : ScalarCoreVSimdGprGprIntrinsic;
def int_riscv_cv_simd_ # NAME # _b : ScalarCoreVSimdGprGprIntrinsic;
}

multiclass ScalarCoreVSimdGprGprGprIntrinsicHB {
def int_riscv_cv_simd_ # NAME # _h : ScalarCoreVSimdGprGprGprIntrinsic;
def int_riscv_cv_simd_ # NAME # _b : ScalarCoreVSimdGprGprGprIntrinsic;
}

multiclass ScalarCoreVSimdGprGprIntrinsicDiv {
def int_riscv_cv_simd_ # NAME # _div2 : ScalarCoreVSimdGprGprIntrinsic;
def int_riscv_cv_simd_ # NAME # _div4 : ScalarCoreVSimdGprGprIntrinsic;
def int_riscv_cv_simd_ # NAME # _div8 : ScalarCoreVSimdGprGprIntrinsic;
}

multiclass ScalarCoreVSimdGprImmIntrinsicHB {
def int_riscv_cv_simd_ # NAME # _h : ScalarCoreVSimdGprImmIntrinsic;
def int_riscv_cv_simd_ # NAME # _b : ScalarCoreVSimdGprImmIntrinsic;
}

multiclass CoreVSimdBinary <bit exclude_h = false> {
if exclude_h then {
def int_riscv_cv_simd_ # NAME # _b : ScalarCoreVSimdGprGprIntrinsic;
} else {
defm NAME : ScalarCoreVSimdGprGprIntrinsicHB;
}
defm NAME # _sc : ScalarCoreVSimdGprGprIntrinsicHB;
}

multiclass CoreVSimdTernary {
defm NAME : ScalarCoreVSimdGprGprGprIntrinsicHB;
defm NAME # _sc : ScalarCoreVSimdGprGprGprIntrinsicHB;
}

let TargetPrefix = "riscv" in {
def int_riscv_cv_bitmanip_extract : ScalarCoreVBitManipGprGprIntrinsic;
def int_riscv_cv_bitmanip_extractu : ScalarCoreVBitManipGprGprIntrinsic;
Expand Down Expand Up @@ -90,4 +154,64 @@ let TargetPrefix = "riscv" in {
def int_riscv_cv_mac_machhuRN : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_macsRN : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_machhsRN : ScalarCoreVMacGprGprGprImmIntrinsic;

defm add : CoreVSimdBinary<true>;
def int_riscv_cv_simd_add_h : ScalarCoreVSimdGprGprImmIntrinsic;
defm sub : CoreVSimdBinary<true>;
def int_riscv_cv_simd_sub_h : ScalarCoreVSimdGprGprImmIntrinsic;
defm avg : CoreVSimdBinary;
defm avgu : CoreVSimdBinary;
defm min : CoreVSimdBinary;
defm minu : CoreVSimdBinary;
defm max : CoreVSimdBinary;
defm maxu : CoreVSimdBinary;
defm srl : CoreVSimdBinary;
defm sra : CoreVSimdBinary;
defm sll : CoreVSimdBinary;
defm or : CoreVSimdBinary;
defm xor : CoreVSimdBinary;
defm and : CoreVSimdBinary;

defm abs : ScalarCoreVSimdGprIntrinsicHB;

defm dotup : CoreVSimdBinary;
defm dotusp : CoreVSimdBinary;
defm dotsp : CoreVSimdBinary;
defm sdotup : CoreVSimdTernary;
defm sdotusp : CoreVSimdTernary;
defm sdotsp : CoreVSimdTernary;

defm extract : ScalarCoreVSimdGprImmIntrinsicHB;
defm extractu : ScalarCoreVSimdGprImmIntrinsicHB;
def int_riscv_cv_simd_insert_b : ScalarCoreVSimdGprGprImmIntrinsic;
def int_riscv_cv_simd_insert_h : ScalarCoreVSimdGprGprImmIntrinsic;


defm shuffle : ScalarCoreVSimdGprGprIntrinsicHB;
def int_riscv_cv_simd_shuffle_sci_h : ScalarCoreVSimdGprImmIntrinsic;
def int_riscv_cv_simd_shuffle_sci_b : ScalarCoreVSimdGprImmIntrinsic;
defm shuffle2 : ScalarCoreVSimdGprGprGprIntrinsicHB;

def int_riscv_cv_simd_packhi_h : ScalarCoreVSimdGprGprIntrinsic;
def int_riscv_cv_simd_packlo_h : ScalarCoreVSimdGprGprIntrinsic;
def int_riscv_cv_simd_packhi_b : ScalarCoreVSimdGprGprGprIntrinsic;
def int_riscv_cv_simd_packlo_b : ScalarCoreVSimdGprGprGprIntrinsic;

defm cmpeq : CoreVSimdBinary;
defm cmpne : CoreVSimdBinary;
defm cmpgt : CoreVSimdBinary;
defm cmpge : CoreVSimdBinary;
defm cmplt : CoreVSimdBinary;
defm cmple : CoreVSimdBinary;
defm cmpgtu : CoreVSimdBinary;
defm cmpgeu : CoreVSimdBinary;
defm cmpltu : CoreVSimdBinary;
defm cmpleu : CoreVSimdBinary;

def int_riscv_cv_simd_cplxmul_r : ScalarCoreVSimdGprGprGprImmIntrinsic;
def int_riscv_cv_simd_cplxmul_i : ScalarCoreVSimdGprGprGprImmIntrinsic;

def int_riscv_cv_simd_cplxconj : ScalarCoreVSimdGprIntrinsic;

def int_riscv_cv_simd_subrotmj : ScalarCoreVSimdGprGprImmIntrinsic;
} // TargetPrefix = "riscv"
20 changes: 20 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -20316,6 +20316,24 @@ static MachineBasicBlock *emitFROUND(MachineInstr &MI, MachineBasicBlock *MBB,
return DoneMBB;
}

static MachineBasicBlock *
emitCV_SHUFFLE_SCI_B(MachineInstr &MI, MachineBasicBlock *MBB,
const RISCVSubtarget &Subtarget) {
DebugLoc DL = MI.getDebugLoc();
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg();
uint8_t Imm = MI.getOperand(2).getImm();
const unsigned Opcodes[] = {
RISCV::CV_SHUFFLEI0_SCI_B, RISCV::CV_SHUFFLEI1_SCI_B,
RISCV::CV_SHUFFLEI2_SCI_B, RISCV::CV_SHUFFLEI3_SCI_B};
const RISCVInstrInfo &TII = *Subtarget.getInstrInfo();
BuildMI(*MBB, MI, DL, TII.get(Opcodes[Imm >> 6]), DstReg)
.addReg(SrcReg)
.addImm(SignExtend64<6>(Imm));
MI.eraseFromParent();
return MBB;
}

MachineBasicBlock *
RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *BB) const {
Expand Down Expand Up @@ -20393,6 +20411,8 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
return emitFROUND(MI, BB, Subtarget);
case RISCV::PROBED_STACKALLOC_DYN:
return emitDynamicProbedAlloc(MI, BB);
case RISCV::PseudoCV_SHUFFLE_SCI_B:
return emitCV_SHUFFLE_SCI_B(MI, BB, Subtarget);
case TargetOpcode::STATEPOINT:
// STATEPOINT is a pseudo instruction which has no implicit defs/uses
// while jal call instruction (where statepoint will be lowered at the end)
Expand Down
Loading