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@broxigarchen broxigarchen commented Dec 5, 2024

Enable GISEL selection with True16 flow for uaddsat and usubsat.

This patch includes:

  1. Added VGPR_16_Lo128/VGPR_16 to register bank and update register info for recognizing 16bit regclass id and bit width
  2. Updated CodeGen pattern for BUILD_VECTOR and support true16/fake16 flow selection

@broxigarchen broxigarchen changed the title [AMDGPU][True16][CodeGen] globalIsel supporting saddsat and ssubsat selection in true16 flow [AMDGPU][True16][CodeGen] saddsat and ssubsat selection in true16 flow globalIsel Dec 5, 2024
@broxigarchen broxigarchen changed the title [AMDGPU][True16][CodeGen] saddsat and ssubsat selection in true16 flow globalIsel [AMDGPU][True16][CodeGen] saddsat and ssubsat selection in true16 flow globalISel Dec 5, 2024
@broxigarchen broxigarchen changed the title [AMDGPU][True16][CodeGen] saddsat and ssubsat selection in true16 flow globalISel [AMDGPU][True16][CodeGen] uaddsat and usubsat selection in true16 flow globalISel Dec 5, 2024
@broxigarchen broxigarchen force-pushed the main-merge-true16-codegen-addsub branch 2 times, most recently from 83532f0 to f0e9e82 Compare December 5, 2024 20:57
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github-actions bot commented Dec 5, 2024

✅ With the latest revision this PR passed the C/C++ code formatter.

@broxigarchen broxigarchen changed the title [AMDGPU][True16][CodeGen] uaddsat and usubsat selection in true16 flow globalISel [AMDGPU][True16][CodeGen] uaddsat/usubsat globalISel for true16 format Dec 5, 2024
@broxigarchen broxigarchen force-pushed the main-merge-true16-codegen-addsub branch from d0d75a9 to 33ee6ab Compare February 21, 2025 21:06
@broxigarchen broxigarchen force-pushed the main-merge-true16-codegen-addsub branch from 33ee6ab to 8f73cc4 Compare February 21, 2025 21:07
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