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[AMDGPU][True16][MC] true16 for v_alignbit_b32 #119409

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Merged
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Feb 27, 2025
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[AMDGPU][True16][MC] true16 for v_alignbit_b32 #119409

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115 changes: 98 additions & 17 deletions llvm/lib/Target/AMDGPU/SIInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2499,6 +2499,7 @@ def : AMDGPUPat <
$src1), sub1)
>;

let True16Predicate = NotHasTrue16BitInsts in {
def : ROTRPattern <V_ALIGNBIT_B32_e64>;

def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
Expand All @@ -2508,6 +2509,42 @@ def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
(V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
} // end True16Predicate = NotHasTrue16BitInsts

let True16Predicate = UseFakeTrue16Insts in {
def : GCNPat <
(rotr i32:$src0, i32:$src1),
(V_ALIGNBIT_B32_fake16_e64 /* src0_modifiers */ 0, $src0,
/* src1_modifiers */ 0, $src0,
/* src2_modifiers */ 0,
$src1, /* clamp */ 0, /* op_sel */ 0)
>;

def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
(V_ALIGNBIT_B32_fake16_e64 0, /* src0_modifiers */
(i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
0, /* src1_modifiers */
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)),
0, /* src2_modifiers */
$src1, /* clamp */ 0, /* op_sel */ 0)
>;

def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
(V_ALIGNBIT_B32_fake16_e64 0, /* src0_modifiers */
(i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
0, /* src1_modifiers */
(i32 (EXTRACT_SUBREG (i64 $src0), sub0)),
0, /* src2_modifiers */
$src1, /* clamp */ 0, /* op_sel */ 0)
>;

def : GCNPat<(fshr i32:$src0, i32:$src1, i32:$src2),
(V_ALIGNBIT_B32_fake16_e64 /* src0_modifiers */ 0, $src0,
/* src1_modifiers */ 0, $src1,
/* src2_modifiers */ 0,
$src2, /* clamp */ 0, /* op_sel */ 0)
>;
} // end True16Predicate = UseFakeTrue16Insts

/********** ====================== **********/
/********** Indirect addressing **********/
Expand Down Expand Up @@ -3015,35 +3052,69 @@ def : GCNPat <
(i32 (EXTRACT_SUBREG $a, sub0))), (i32 1))
>;

let True16Predicate = NotHasTrue16BitInsts in
def : GCNPat <
(i32 (bswap i32:$a)),
(V_BFI_B32_e64 (S_MOV_B32 (i32 0x00ff00ff)),
(V_ALIGNBIT_B32_e64 VSrc_b32:$a, VSrc_b32:$a, (i32 24)),
(V_ALIGNBIT_B32_e64 VSrc_b32:$a, VSrc_b32:$a, (i32 8)))
>;

// FIXME: This should have been narrowed to i32 during legalization.
// This pattern should also be skipped for GlobalISel
let True16Predicate = UseFakeTrue16Insts in
def : GCNPat <
(i32 (bswap i32:$a)),
(V_BFI_B32_e64 (S_MOV_B32 (i32 0x00ff00ff)),
(V_ALIGNBIT_B32_fake16_e64 0, /* src0_modifiers */
VSrc_b32:$a,
0, /* src1_modifiers */
VSrc_b32:$a,
0, /* src2_modifiers */
(i32 24), /* clamp */ 0, /* op_sel */ 0),
(V_ALIGNBIT_B32_fake16_e64 0, /* src0_modifiers */
VSrc_b32:$a,
0, /* src1_modifiers */
VSrc_b32:$a,
0, /* src2_modifiers */
(i32 8), /* clamp */ 0, /* op_sel */ 0))
>;

class AlignBit32Inst<dag op1, dag op2, dag op3, bit isTrue16> {
defvar inst = !if(isTrue16, V_ALIGNBIT_B32_fake16_e64, V_ALIGNBIT_B32_e64);
defvar NoMods = !if(isTrue16, (inst 0), (inst));
dag ret = !con(NoMods, (inst op1), NoMods, (inst op2),
NoMods, (inst op3), NoMods, NoMods);
}

multiclass bswapi64ExtPat<bit hasTrue16> {
def : GCNPat <
(i64 (bswap i64:$a)),
(REG_SEQUENCE VReg_64,
(V_BFI_B32_e64 (S_MOV_B32 (i32 0x00ff00ff)),
(V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
(i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
(i32 24)),
(V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
(i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
(i32 8))),
AlignBit32Inst<(i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
(i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
(i32 24), hasTrue16>.ret,
AlignBit32Inst<(i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
(i32 (EXTRACT_SUBREG VReg_64:$a, sub1)),
(i32 8), hasTrue16>.ret),
sub0,
(V_BFI_B32_e64 (S_MOV_B32 (i32 0x00ff00ff)),
(V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
(i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
(i32 24)),
(V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
(i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
(i32 8))),
AlignBit32Inst<(i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
(i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
(i32 24), hasTrue16>.ret,
AlignBit32Inst<(i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
(i32 (EXTRACT_SUBREG VReg_64:$a, sub0)),
(i32 8), hasTrue16>.ret),
sub1)
>;
}

// FIXME: This should have been narrowed to i32 during legalization.
// This pattern should also be skipped for GlobalISel
let True16Predicate = NotHasTrue16BitInsts in
defm : bswapi64ExtPat</*hasTrue16*/0>;

let True16Predicate = UseFakeTrue16Insts in
defm : bswapi64ExtPat</*hasTrue16*/1>;

// FIXME: The AddedComplexity should not be needed, but in GlobalISel
// the BFI pattern ends up taking precedence without it.
Expand Down Expand Up @@ -3456,8 +3527,7 @@ def : GCNPat <

// Take the upper 16 bits from V[0] and the lower 16 bits from V[1]
// Special case, can use V_ALIGNBIT (always uses encoded literal)
foreach p = [NotHasTrue16BitInsts, UseFakeTrue16Insts] in
let True16Predicate = p in {
let True16Predicate = NotHasTrue16BitInsts in
def : GCNPat <
(vecTy (DivergentBinFrag<build_vector>
(Ty !if(!eq(Ty, i16),
Expand All @@ -3467,7 +3537,19 @@ def : GCNPat <
(V_ALIGNBIT_B32_e64 VGPR_32:$b, VGPR_32:$a, (i32 16))
>;

let True16Predicate = UseFakeTrue16Insts in
def : GCNPat <
(vecTy (DivergentBinFrag<build_vector>
(Ty !if(!eq(Ty, i16),
(Ty (trunc (srl VGPR_32:$a, (i32 16)))),
(Ty (bitconvert (i16 (trunc (srl VGPR_32:$a, (i32 16)))))))),
(Ty VGPR_32:$b))),
(V_ALIGNBIT_B32_fake16_e64 0, VGPR_32:$b, 0, VGPR_32:$a, 0, (i16 16), 0, 0)
>;

// Take the upper 16 bits from each VGPR_32 and concat them
foreach p = [NotHasTrue16BitInsts, UseFakeTrue16Insts] in
let True16Predicate = p in
Comment on lines +3551 to +3552
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@kosarev kosarev Mar 3, 2025

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@broxigarchen This causes lots of test changes downstream; please cherry-pick this patch there.

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@broxigarchen broxigarchen Mar 3, 2025

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Ack

def : GCNPat <
(vecTy (DivergentBinFrag<build_vector>
(Ty !if(!eq(Ty, i16),
Expand All @@ -3478,7 +3560,6 @@ def : GCNPat <
(Ty (bitconvert (i16 (trunc (srl VGPR_32:$b, (i32 16)))))))))),
(V_PERM_B32_e64 VGPR_32:$b, VGPR_32:$a, (S_MOV_B32 (i32 0x07060302)))
>;
}

} // end foreach Ty

Expand Down
9 changes: 6 additions & 3 deletions llvm/lib/Target/AMDGPU/VOP3Instructions.td
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Expand Up @@ -211,9 +211,12 @@ defm V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>,
defm V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>;
defm V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>;
defm V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>;
defm V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, fshr>;
defm V_ALIGNBIT_B32 : VOP3Inst_t16_with_profiles <"v_alignbit_b32",
VOP3_Profile<VOP_I32_I32_I32_I32>,
VOP3_Profile_True16<VOP_I32_I32_I32_I16, VOP3_OPSEL>,
VOP3_Profile_Fake16<VOP_I32_I32_I32_I16, VOP3_OPSEL>,
fshr, null_frag>;

let True16Predicate = NotHasTrue16BitInsts in
defm V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>;
let True16Predicate = UseRealTrue16Insts in
defm V_ALIGNBYTE_B32_t16 : VOP3Inst <"v_alignbyte_b32_t16", VOP3_Profile_True16<VOP_I32_I32_I32_I16, VOP3_OPSEL>>;
Expand Down Expand Up @@ -1726,7 +1729,7 @@ defm V_BFI_B32 : VOP3_Realtriple_gfx11_gfx12<0x212>;
defm V_FMA_F32 : VOP3_Realtriple_gfx11_gfx12<0x213>;
defm V_FMA_F64 : VOP3_Real_Base_gfx11_gfx12<0x214>;
defm V_LERP_U8 : VOP3_Realtriple_gfx11_gfx12<0x215>;
defm V_ALIGNBIT_B32 : VOP3_Realtriple_gfx11_gfx12<0x216>;
defm V_ALIGNBIT_B32 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x216, "v_alignbit_b32">;
defm V_ALIGNBYTE_B32 : VOP3_Realtriple_t16_and_fake16_gfx11_gfx12<0x217, "v_alignbyte_b32">;
defm V_MULLIT_F32 : VOP3_Realtriple_gfx11_gfx12<0x218>;
defm V_MIN3_F32 : VOP3_Realtriple_gfx11<0x219>;
Expand Down
11 changes: 10 additions & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
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Expand Up @@ -3,7 +3,7 @@
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX11 %s

---

Expand All @@ -23,6 +23,15 @@ body: |
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GCN-NEXT: [[V_ALIGNBIT_B32_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_e64 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_e64_]]
;
; GFX11-LABEL: name: fshr_s32
; GFX11: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX11-NEXT: [[V_ALIGNBIT_B32_fake16_e64_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32_fake16_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
; GFX11-NEXT: S_ENDPGM 0, implicit [[V_ALIGNBIT_B32_fake16_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2
Expand Down
28 changes: 19 additions & 9 deletions llvm/test/CodeGen/AMDGPU/bswap.ll
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Expand Up @@ -737,15 +737,25 @@ define i64 @v_bswap_i48(i64 %src) {
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_bswap_i48:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_perm_b32 v2, 0, v0, 0x10203
; GFX11-NEXT: v_perm_b32 v0, 0, v1, 0x10203
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-NEXT: v_alignbit_b32 v0, v2, v0, 16
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-REAL16-LABEL: v_bswap_i48:
; GFX11-REAL16: ; %bb.0:
; GFX11-REAL16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-REAL16-NEXT: v_perm_b32 v2, 0, v0, 0x10203
; GFX11-REAL16-NEXT: v_perm_b32 v1, 0, v1, 0x10203
; GFX11-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-REAL16-NEXT: v_lshrrev_b64 v[0:1], 16, v[1:2]
; GFX11-REAL16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-REAL16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_bswap_i48:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v2, 0, v0, 0x10203
; GFX11-FAKE16-NEXT: v_perm_b32 v0, 0, v1, 0x10203
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, v2, v0, 16
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%trunc = trunc i64 %src to i48
%bswap = call i48 @llvm.bswap.i48(i48 %trunc)
%zext = zext i48 %bswap to i64
Expand Down
29 changes: 16 additions & 13 deletions llvm/test/MC/AMDGPU/gfx11_asm_vop3.s
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Expand Up @@ -416,11 +416,11 @@ v_alignbit_b32 v5, s1, v255, s3
v_alignbit_b32 v5, s105, s105, s105
// GFX11: v_alignbit_b32 v5, s105, s105, s105 ; encoding: [0x05,0x00,0x16,0xd6,0x69,0xd2,0xa4,0x01]

v_alignbit_b32 v5, vcc_lo, ttmp15, v3
// GFX11: v_alignbit_b32 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]
v_alignbit_b32 v5, vcc_lo, ttmp15, v3.l
// GFX11: v_alignbit_b32 v5, vcc_lo, ttmp15, v3.l ; encoding: [0x05,0x00,0x16,0xd6,0x6a,0xf6,0x0c,0x04]

v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255
// GFX11: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]
v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.l
// GFX11: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.l ; encoding: [0x05,0x00,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]

v_alignbit_b32 v5, ttmp15, src_scc, ttmp15
// GFX11: v_alignbit_b32 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x00,0x16,0xd6,0x7b,0xfa,0xed,0x01]
Expand Down Expand Up @@ -449,6 +449,9 @@ v_alignbit_b32 v5, src_scc, vcc_lo, -1
v_alignbit_b32 v255, 0xaf123456, vcc_hi, null
// GFX11: v_alignbit_b32 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x00,0x16,0xd6,0xff,0xd6,0xf0,0x01,0x56,0x34,0x12,0xaf]

v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.h
// GFX11: v_alignbit_b32 v5, vcc_hi, 0xaf123456, v255.h op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x16,0xd6,0x6b,0xfe,0xfd,0x07,0x56,0x34,0x12,0xaf]

v_alignbyte_b32 v5, v1, v2, s3
// GFX11: v_alignbyte_b32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x17,0xd6,0x01,0x05,0x0e,0x00]

Expand Down Expand Up @@ -543,13 +546,13 @@ v_and_b16 v255.l, 0xfe0b, vcc_hi
// GFX11: v_and_b16 v255.l, 0xfe0b, vcc_hi ; encoding: [0xff,0x00,0x62,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]

v_and_b16 v5.l, v1.h, v2.l
// GFX11: [0x05,0x08,0x62,0xd7,0x01,0x05,0x02,0x00]
// GFX11: v_and_b16 v5.l, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x62,0xd7,0x01,0x05,0x02,0x00]

v_and_b16 v5.l, v255.l, v255.h
// GFX11: [0x05,0x10,0x62,0xd7,0xff,0xff,0x03,0x00]
// GFX11: v_and_b16 v5.l, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x62,0xd7,0xff,0xff,0x03,0x00]

v_and_b16 v255.h, 0xfe0b, vcc_hi
// GFX11: [0xff,0x40,0x62,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
// GFX11: v_and_b16 v255.h, 0xfe0b, vcc_hi op_sel:[0,0,1] ; encoding: [0xff,0x40,0x62,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]

v_and_or_b32 v5, v1, v2, s3
// GFX11: v_and_or_b32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x57,0xd6,0x01,0x05,0x0e,0x00]
Expand Down Expand Up @@ -5577,13 +5580,13 @@ v_or_b16 v255.l, 0xfe0b, vcc_hi
// GFX11: v_or_b16 v255.l, 0xfe0b, vcc_hi ; encoding: [0xff,0x00,0x63,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]

v_or_b16 v5.l, v1.h, v2.l
// GFX11: [0x05,0x08,0x63,0xd7,0x01,0x05,0x02,0x00]
// GFX11: v_or_b16 v5.l, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x63,0xd7,0x01,0x05,0x02,0x00]

v_or_b16 v5.l, v255.l, v255.h
// GFX11: [0x05,0x10,0x63,0xd7,0xff,0xff,0x03,0x00]
// GFX11: v_or_b16 v5.l, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x63,0xd7,0xff,0xff,0x03,0x00]

v_or_b16 v255.h, 0xfe0b, vcc_hi
// GFX11: [0xff,0x40,0x63,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
// GFX11: v_or_b16 v255.h, 0xfe0b, vcc_hi op_sel:[0,0,1] ; encoding: [0xff,0x40,0x63,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]

v_pack_b32_f16 v5, v1.l, v2.l
// GFX11: v_pack_b32_f16 v5, v1.l, v2.l ; encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x02,0x00]
Expand Down Expand Up @@ -6632,10 +6635,10 @@ v_xor_b16 v255.l, 0xfe0b, vcc_hi
// GFX11: v_xor_b16 v255.l, 0xfe0b, vcc_hi ; encoding: [0xff,0x00,0x64,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]

v_xor_b16 v5.l, v1.h, v2.l
// GFX11: [0x05,0x08,0x64,0xd7,0x01,0x05,0x02,0x00]
// GFX11: v_xor_b16 v5.l, v1.h, v2.l op_sel:[1,0,0] ; encoding: [0x05,0x08,0x64,0xd7,0x01,0x05,0x02,0x00]

v_xor_b16 v5.l, v255.l, v255.h
// GFX11: [0x05,0x10,0x64,0xd7,0xff,0xff,0x03,0x00]
// GFX11: v_xor_b16 v5.l, v255.l, v255.h op_sel:[0,1,0] ; encoding: [0x05,0x10,0x64,0xd7,0xff,0xff,0x03,0x00]

v_xor_b16 v255.h, 0xfe0b, vcc_hi
// GFX11: [0xff,0x40,0x64,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
// GFX11: v_xor_b16 v255.h, 0xfe0b, vcc_hi op_sel:[0,0,1] ; encoding: [0xff,0x40,0x64,0xd7,0xff,0xd6,0x00,0x00,0x0b,0xfe,0x00,0x00]
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