Skip to content

[RISCV][GISel] Port TrailingOnesMask PatLeaf. #119427

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Dec 11, 2024
Merged

[RISCV][GISel] Port TrailingOnesMask PatLeaf. #119427

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
1c83609
[RISCV][GISel] Port TrailingOnesMask PatLeaf.
topperc Dec 10, 2024
518059f
fixup! address review comment:
topperc Dec 11, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
10 changes: 10 additions & 0 deletions llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -134,6 +134,8 @@ class RISCVInstructionSelector : public InstructionSelector {

void renderTrailingZeros(MachineInstrBuilder &MIB, const MachineInstr &MI,
int OpIdx) const;
void renderXLenSubTrailingOnes(MachineInstrBuilder &MIB,
const MachineInstr &MI, int OpIdx) const;

const RISCVSubtarget &STI;
const RISCVInstrInfo &TII;
Expand Down Expand Up @@ -861,6 +863,14 @@ void RISCVInstructionSelector::renderTrailingZeros(MachineInstrBuilder &MIB,
MIB.addImm(llvm::countr_zero(C));
}

void RISCVInstructionSelector::renderXLenSubTrailingOnes(
MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const {
assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 &&
"Expected G_CONSTANT");
uint64_t C = MI.getOperand(1).getCImm()->getZExtValue();
MIB.addImm(Subtarget->getXLen() - llvm::countr_one(C));
}

const TargetRegisterClass *RISCVInstructionSelector::getRegClassForTypeOnBank(
LLT Ty, const RegisterBank &RB) const {
if (RB.getID() == RISCV::GPRBRegBankID) {
Expand Down
12 changes: 11 additions & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -476,6 +476,8 @@ def XLenSubTrailingOnes : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(XLen - TrailingOnes, SDLoc(N),
N->getValueType(0));
}]>;
def GIXLenSubTrailingOnes : GICustomOperandRenderer<"renderXLenSubTrailingOnes">,
GISDNodeXFormEquiv<XLenSubTrailingOnes>;

// Checks if this mask is a non-empty sequence of ones starting at the
// most/least significant bit with the remainder zero and exceeds simm32/simm12.
Expand All @@ -489,7 +491,15 @@ def TrailingOnesMask : PatLeaf<(imm), [{
if (!N->hasOneUse())
return false;
return !isInt<12>(N->getSExtValue()) && isMask_64(N->getZExtValue());
}], XLenSubTrailingOnes>;
}], XLenSubTrailingOnes> {
let GISelPredicateCode = [{
if (!MRI.hasOneNonDBGUse(MI.getOperand(0).getReg()))
return false;
const auto &MO = MI.getOperand(1);
return !isInt<12>(MO.getCImm()->getSExtValue()) &&
isMask_64(MO.getCImm()->getZExtValue());
}];
}

// Similar to LeadingOnesMask, but only consider leading ones in the lower 32
// bits.
Expand Down
34 changes: 16 additions & 18 deletions llvm/test/CodeGen/RISCV/GlobalISel/double-arith.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -161,19 +161,19 @@ define double @fsgnj_d(double %a, double %b) nounwind {
; RV32I-LABEL: fsgnj_d:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: addi a4, a2, -1
; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: fsgnj_d:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, -1
; RV64I-NEXT: slli a3, a2, 63
; RV64I-NEXT: srli a2, a2, 1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: slli a2, a2, 63
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
%1 = call double @llvm.copysign.f64(double %a, double %b)
Expand Down Expand Up @@ -241,21 +241,21 @@ define double @fsgnjn_d(double %a, double %b) nounwind {
; RV32I-LABEL: fsgnjn_d:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: xor a3, a3, a2
; RV32I-NEXT: addi a4, a2, -1
; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: fsgnjn_d:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, -1
; RV64I-NEXT: slli a3, a2, 63
; RV64I-NEXT: srli a2, a2, 1
; RV64I-NEXT: xor a1, a1, a3
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: slli a2, a2, 63
; RV64I-NEXT: xor a1, a1, a2
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
%1 = fneg double %b
Expand All @@ -281,9 +281,8 @@ define double @fabs_d(double %a, double %b) nounwind {
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __adddf3
; RV32I-NEXT: mv a3, a1
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: call __adddf3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -296,9 +295,8 @@ define double @fabs_d(double %a, double %b) nounwind {
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __adddf3
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: li a0, -1
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: call __adddf3
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down
20 changes: 8 additions & 12 deletions llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -787,27 +787,24 @@ define zeroext i16 @fcvt_wu_s_i16(double %a) nounwind {
; RV32IFD-LABEL: fcvt_wu_s_i16:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV32IFD-NEXT: lui a1, 16
; RV32IFD-NEXT: addi a1, a1, -1
; RV32IFD-NEXT: and a0, a0, a1
; RV32IFD-NEXT: slli a0, a0, 16
; RV32IFD-NEXT: srli a0, a0, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_wu_s_i16:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
; RV64IFD-NEXT: lui a1, 16
; RV64IFD-NEXT: addiw a1, a1, -1
; RV64IFD-NEXT: and a0, a0, a1
; RV64IFD-NEXT: slli a0, a0, 48
; RV64IFD-NEXT: srli a0, a0, 48
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __fixunsdfsi
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -817,9 +814,8 @@ define zeroext i16 @fcvt_wu_s_i16(double %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunsdfsi
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
Expand Down
38 changes: 17 additions & 21 deletions llvm/test/CodeGen/RISCV/GlobalISel/double-intrinsics.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -631,16 +631,14 @@ define double @fabs_f64(double %a) nounwind {
;
; RV32I-LABEL: fabs_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: addi a2, a2, -1
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fabs_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: srli a1, a1, 1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: ret
%1 = call double @llvm.fabs.f64(double %a)
ret double %1
Expand Down Expand Up @@ -715,19 +713,19 @@ define double @copysign_f64(double %a, double %b) nounwind {
; RV32I-LABEL: copysign_f64:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: addi a4, a2, -1
; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: copysign_f64:
; RV64I: # %bb.0:
; RV64I-NEXT: li a2, -1
; RV64I-NEXT: slli a3, a2, 63
; RV64I-NEXT: srli a2, a2, 1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: slli a2, a2, 63
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
%1 = call double @llvm.copysign.f64(double %a, double %b)
Expand Down Expand Up @@ -1039,10 +1037,9 @@ define i1 @isnan_d_fpclass(double %x) {
;
; RV32I-LABEL: isnan_d_fpclass:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: addi a3, a2, -1
; RV32I-NEXT: lui a2, 524032
; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: beq a1, a2, .LBB25_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a0, a2, a1
Expand All @@ -1053,12 +1050,11 @@ define i1 @isnan_d_fpclass(double %x) {
;
; RV64I-LABEL: isnan_d_fpclass:
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: li a2, 2047
; RV64I-NEXT: srli a1, a1, 1
; RV64I-NEXT: slli a2, a2, 52
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: sltu a0, a2, a0
; RV64I-NEXT: li a1, 2047
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: slli a1, a1, 52
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: sltu a0, a1, a0
; RV64I-NEXT: ret
%1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; nan
ret i1 %1
Expand Down
30 changes: 14 additions & 16 deletions llvm/test/CodeGen/RISCV/GlobalISel/float-arith.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -161,17 +161,17 @@ define float @fsgnj_s(float %a, float %b) nounwind {
; RV32I-LABEL: fsgnj_s:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: addi a3, a2, -1
; RV32I-NEXT: and a0, a0, a3
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fsgnj_s:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 524288
; RV64I-NEXT: addiw a3, a2, -1
; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: slli a0, a0, 33
; RV64I-NEXT: srli a0, a0, 33
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
Expand Down Expand Up @@ -238,11 +238,11 @@ define float @fsgnjn_s(float %a, float %b) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: call __addsf3
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: slli s0, s0, 1
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: addi a2, a1, -1
; RV32I-NEXT: and a2, s0, a2
; RV32I-NEXT: srli s0, s0, 1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a0, s0, a0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -256,11 +256,11 @@ define float @fsgnjn_s(float %a, float %b) nounwind {
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: call __addsf3
; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: slli s0, s0, 33
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: addiw a2, a1, -1
; RV64I-NEXT: and a2, s0, a2
; RV64I-NEXT: srli s0, s0, 33
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, s0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand All @@ -287,9 +287,8 @@ define float @fabs_s(float %a, float %b) nounwind {
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __addsf3
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: call __addsf3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -301,9 +300,8 @@ define float @fabs_s(float %a, float %b) nounwind {
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __addsf3
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui a0, 524288
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: slli a0, a0, 33
; RV64I-NEXT: srli a0, a0, 33
; RV64I-NEXT: call __addsf3
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down
20 changes: 8 additions & 12 deletions llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -722,27 +722,24 @@ define zeroext i16 @fcvt_wu_s_i16(float %a) nounwind {
; RV32IF-LABEL: fcvt_wu_s_i16:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IF-NEXT: lui a1, 16
; RV32IF-NEXT: addi a1, a1, -1
; RV32IF-NEXT: and a0, a0, a1
; RV32IF-NEXT: slli a0, a0, 16
; RV32IF-NEXT: srli a0, a0, 16
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_wu_s_i16:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: lui a1, 16
; RV64IF-NEXT: addiw a1, a1, -1
; RV64IF-NEXT: and a0, a0, a1
; RV64IF-NEXT: slli a0, a0, 48
; RV64IF-NEXT: srli a0, a0, 48
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_i16:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __fixunssfsi
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -752,9 +749,8 @@ define zeroext i16 @fcvt_wu_s_i16(float %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunssfsi
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
Expand Down
Loading
Loading