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[RISCV] Optimize (slli (srli (slli X, C1), C1), C2) -> (srli (slli X, C1), C1-C2) #119567

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Merged
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Dec 12, 2024
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[RISCV] Optimize (slli (srli (slli X, C1), C1), C2) -> (srli (slli X, C1), C1-C2) #119567

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263e5a1
[RISCV][test] Add and-shl.ll
pfusik Dec 11, 2024
9bc1c75
[RISCV] Fold (slli (srli (slli X, C1), C1), C2) -> (srli (slli X, C1)…
pfusik Dec 11, 2024
e907baa
fixup! [RISCV] Fold (slli (srli (slli X, C1), C1), C2) -> (srli (slli…
pfusik Dec 11, 2024
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23 changes: 21 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Expand Up @@ -1026,13 +1026,13 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
unsigned ShAmt = N1C->getZExtValue();
uint64_t Mask = N0.getConstantOperandVal(1);

// Optimize (shl (and X, C2), C) -> (slli (srliw X, C3), C3+C) where C2 has
// 32 leading zeros and C3 trailing zeros.
if (ShAmt <= 32 && isShiftedMask_64(Mask)) {
unsigned XLen = Subtarget->getXLen();
unsigned LeadingZeros = XLen - llvm::bit_width(Mask);
unsigned TrailingZeros = llvm::countr_zero(Mask);
if (TrailingZeros > 0 && LeadingZeros == 32) {
// Optimize (shl (and X, C2), C) -> (slli (srliw X, C3), C3+C)
// where C2 has 32 leading zeros and C3 trailing zeros.
SDNode *SRLIW = CurDAG->getMachineNode(
RISCV::SRLIW, DL, VT, N0->getOperand(0),
CurDAG->getTargetConstant(TrailingZeros, DL, VT));
Expand All @@ -1042,6 +1042,25 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
ReplaceNode(Node, SLLI);
return;
}
if (TrailingZeros == 0 && LeadingZeros > ShAmt &&
XLen - LeadingZeros > 11 && LeadingZeros != 32) {
// Optimize (shl (and X, C2), C) -> (srli (slli X, C4), C4-C)
// where C2 has C4 leading zeros and no trailing zeros.
// This is profitable if the "and" was to be lowered to
// (srli (slli X, C4), C4) and not (andi X, C2).
// For "LeadingZeros == 32":
// - with Zba it's just (slli.uw X, C)
// - without Zba a tablegen pattern applies the very same
// transform as we would have done here
SDNode *SLLI = CurDAG->getMachineNode(
RISCV::SLLI, DL, VT, N0->getOperand(0),
CurDAG->getTargetConstant(LeadingZeros, DL, VT));
SDNode *SRLI = CurDAG->getMachineNode(
RISCV::SRLI, DL, VT, SDValue(SLLI, 0),
CurDAG->getTargetConstant(LeadingZeros - ShAmt, DL, VT));
ReplaceNode(Node, SRLI);
return;
}
}
break;
}
Expand Down
79 changes: 79 additions & 0 deletions llvm/test/CodeGen/RISCV/and-shl.ll
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@@ -0,0 +1,79 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I

define i32 @and_0xfff_shl_2(i32 %x) {
; RV32I-LABEL: and_0xfff_shl_2:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 20
; RV32I-NEXT: srli a0, a0, 18
; RV32I-NEXT: ret
;
; RV64I-LABEL: and_0xfff_shl_2:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 52
; RV64I-NEXT: srli a0, a0, 50
; RV64I-NEXT: ret
%a = and i32 %x, 4095
%s = shl i32 %a, 2
ret i32 %s
}

define i32 @and_0x7ff_shl_2(i32 %x) {
; RV32I-LABEL: and_0x7ff_shl_2:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 2047
; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: ret
;
; RV64I-LABEL: and_0x7ff_shl_2:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 2047
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: ret
%a = and i32 %x, 2047
%s = shl i32 %a, 2
ret i32 %s
}

define i64 @and_0xffffffff_shl_2(i64 %x) {
; RV32I-LABEL: and_0xffffffff_shl_2:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 2
; RV32I-NEXT: srli a1, a0, 30
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: and_0xffffffff_shl_2:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 30
; RV64I-NEXT: ret
%a = and i64 %x, 4294967295
%s = shl i64 %a, 2
ret i64 %s
}

define i32 @and_0xfff_shl_2_multi_use(i32 %x) {
; RV32I-LABEL: and_0xfff_shl_2_multi_use:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 20
; RV32I-NEXT: srli a0, a0, 20
; RV32I-NEXT: slli a1, a0, 2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: and_0xfff_shl_2_multi_use:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 52
; RV64I-NEXT: srli a0, a0, 52
; RV64I-NEXT: slli a1, a0, 2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
%a = and i32 %x, 4095
%s = shl i32 %a, 2
%r = add i32 %a, %s
ret i32 %r
}
176 changes: 84 additions & 92 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
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Expand Up @@ -124,42 +124,40 @@ define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) {
; ZVFH32: # %bb.0:
; ZVFH32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFH32-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFH32-NEXT: lui a1, 8
; ZVFH32-NEXT: vslidedown.vi v8, v9, 2
; ZVFH32-NEXT: vmv.x.s a2, v9
; ZVFH32-NEXT: addi a1, a1, -1
; ZVFH32-NEXT: vmv.x.s a1, v9
; ZVFH32-NEXT: vslidedown.vi v9, v9, 1
; ZVFH32-NEXT: vmv.x.s a3, v8
; ZVFH32-NEXT: and a2, a2, a1
; ZVFH32-NEXT: vmv.x.s a4, v9
; ZVFH32-NEXT: and a1, a4, a1
; ZVFH32-NEXT: slli a4, a3, 17
; ZVFH32-NEXT: slli a3, a3, 30
; ZVFH32-NEXT: srli a4, a4, 19
; ZVFH32-NEXT: slli a1, a1, 15
; ZVFH32-NEXT: or a2, a2, a3
; ZVFH32-NEXT: or a1, a2, a1
; ZVFH32-NEXT: vmv.x.s a2, v8
; ZVFH32-NEXT: slli a1, a1, 17
; ZVFH32-NEXT: srli a1, a1, 17
; ZVFH32-NEXT: slli a3, a2, 30
; ZVFH32-NEXT: or a1, a1, a3
; ZVFH32-NEXT: vmv.x.s a3, v9
; ZVFH32-NEXT: slli a2, a2, 17
; ZVFH32-NEXT: slli a3, a3, 17
; ZVFH32-NEXT: srli a2, a2, 19
; ZVFH32-NEXT: srli a3, a3, 2
; ZVFH32-NEXT: or a1, a1, a3
; ZVFH32-NEXT: sw a1, 0(a0)
; ZVFH32-NEXT: sh a4, 4(a0)
; ZVFH32-NEXT: sh a2, 4(a0)
; ZVFH32-NEXT: ret
;
; ZVFH64-LABEL: fp2si_v3f32_v3i15:
; ZVFH64: # %bb.0:
; ZVFH64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFH64-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFH64-NEXT: lui a1, 8
; ZVFH64-NEXT: vmv.x.s a2, v9
; ZVFH64-NEXT: addiw a1, a1, -1
; ZVFH64-NEXT: vmv.x.s a1, v9
; ZVFH64-NEXT: vslidedown.vi v8, v9, 1
; ZVFH64-NEXT: vslidedown.vi v9, v9, 2
; ZVFH64-NEXT: and a2, a2, a1
; ZVFH64-NEXT: vmv.x.s a3, v8
; ZVFH64-NEXT: and a1, a3, a1
; ZVFH64-NEXT: slli a1, a1, 49
; ZVFH64-NEXT: vmv.x.s a2, v8
; ZVFH64-NEXT: vmv.x.s a3, v9
; ZVFH64-NEXT: srli a1, a1, 49
; ZVFH64-NEXT: slli a2, a2, 49
; ZVFH64-NEXT: slli a3, a3, 30
; ZVFH64-NEXT: slli a1, a1, 15
; ZVFH64-NEXT: or a2, a2, a3
; ZVFH64-NEXT: or a1, a2, a1
; ZVFH64-NEXT: srli a2, a2, 34
; ZVFH64-NEXT: or a1, a1, a3
; ZVFH64-NEXT: or a1, a1, a2
; ZVFH64-NEXT: slli a2, a1, 19
; ZVFH64-NEXT: srli a2, a2, 51
; ZVFH64-NEXT: sw a1, 0(a0)
Expand All @@ -170,42 +168,40 @@ define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) {
; ZVFHMIN32: # %bb.0:
; ZVFHMIN32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN32-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFHMIN32-NEXT: lui a1, 8
; ZVFHMIN32-NEXT: vslidedown.vi v8, v9, 2
; ZVFHMIN32-NEXT: vmv.x.s a2, v9
; ZVFHMIN32-NEXT: addi a1, a1, -1
; ZVFHMIN32-NEXT: vmv.x.s a1, v9
; ZVFHMIN32-NEXT: vslidedown.vi v9, v9, 1
; ZVFHMIN32-NEXT: vmv.x.s a3, v8
; ZVFHMIN32-NEXT: and a2, a2, a1
; ZVFHMIN32-NEXT: vmv.x.s a4, v9
; ZVFHMIN32-NEXT: and a1, a4, a1
; ZVFHMIN32-NEXT: slli a4, a3, 17
; ZVFHMIN32-NEXT: slli a3, a3, 30
; ZVFHMIN32-NEXT: srli a4, a4, 19
; ZVFHMIN32-NEXT: slli a1, a1, 15
; ZVFHMIN32-NEXT: or a2, a2, a3
; ZVFHMIN32-NEXT: or a1, a2, a1
; ZVFHMIN32-NEXT: vmv.x.s a2, v8
; ZVFHMIN32-NEXT: slli a1, a1, 17
; ZVFHMIN32-NEXT: srli a1, a1, 17
; ZVFHMIN32-NEXT: slli a3, a2, 30
; ZVFHMIN32-NEXT: or a1, a1, a3
; ZVFHMIN32-NEXT: vmv.x.s a3, v9
; ZVFHMIN32-NEXT: slli a2, a2, 17
; ZVFHMIN32-NEXT: slli a3, a3, 17
; ZVFHMIN32-NEXT: srli a2, a2, 19
; ZVFHMIN32-NEXT: srli a3, a3, 2
; ZVFHMIN32-NEXT: or a1, a1, a3
; ZVFHMIN32-NEXT: sw a1, 0(a0)
; ZVFHMIN32-NEXT: sh a4, 4(a0)
; ZVFHMIN32-NEXT: sh a2, 4(a0)
; ZVFHMIN32-NEXT: ret
;
; ZVFHMIN64-LABEL: fp2si_v3f32_v3i15:
; ZVFHMIN64: # %bb.0:
; ZVFHMIN64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN64-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFHMIN64-NEXT: lui a1, 8
; ZVFHMIN64-NEXT: vmv.x.s a2, v9
; ZVFHMIN64-NEXT: addiw a1, a1, -1
; ZVFHMIN64-NEXT: vmv.x.s a1, v9
; ZVFHMIN64-NEXT: vslidedown.vi v8, v9, 1
; ZVFHMIN64-NEXT: vslidedown.vi v9, v9, 2
; ZVFHMIN64-NEXT: and a2, a2, a1
; ZVFHMIN64-NEXT: vmv.x.s a3, v8
; ZVFHMIN64-NEXT: and a1, a3, a1
; ZVFHMIN64-NEXT: slli a1, a1, 49
; ZVFHMIN64-NEXT: vmv.x.s a2, v8
; ZVFHMIN64-NEXT: vmv.x.s a3, v9
; ZVFHMIN64-NEXT: srli a1, a1, 49
; ZVFHMIN64-NEXT: slli a2, a2, 49
; ZVFHMIN64-NEXT: slli a3, a3, 30
; ZVFHMIN64-NEXT: slli a1, a1, 15
; ZVFHMIN64-NEXT: or a2, a2, a3
; ZVFHMIN64-NEXT: or a1, a2, a1
; ZVFHMIN64-NEXT: srli a2, a2, 34
; ZVFHMIN64-NEXT: or a1, a1, a3
; ZVFHMIN64-NEXT: or a1, a1, a2
; ZVFHMIN64-NEXT: slli a2, a1, 19
; ZVFHMIN64-NEXT: srli a2, a2, 51
; ZVFHMIN64-NEXT: sw a1, 0(a0)
Expand All @@ -221,42 +217,40 @@ define <3 x i15> @fp2ui_v3f32_v3i15(<3 x float> %x) {
; ZVFH32: # %bb.0:
; ZVFH32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFH32-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFH32-NEXT: lui a1, 16
; ZVFH32-NEXT: vslidedown.vi v8, v9, 2
; ZVFH32-NEXT: vmv.x.s a2, v9
; ZVFH32-NEXT: addi a1, a1, -1
; ZVFH32-NEXT: vmv.x.s a1, v9
; ZVFH32-NEXT: vslidedown.vi v9, v9, 1
; ZVFH32-NEXT: vmv.x.s a3, v8
; ZVFH32-NEXT: and a2, a2, a1
; ZVFH32-NEXT: vmv.x.s a4, v9
; ZVFH32-NEXT: and a1, a4, a1
; ZVFH32-NEXT: slli a4, a3, 17
; ZVFH32-NEXT: slli a3, a3, 30
; ZVFH32-NEXT: srli a4, a4, 19
; ZVFH32-NEXT: slli a1, a1, 15
; ZVFH32-NEXT: or a2, a2, a3
; ZVFH32-NEXT: or a1, a2, a1
; ZVFH32-NEXT: vmv.x.s a2, v8
; ZVFH32-NEXT: slli a1, a1, 16
; ZVFH32-NEXT: srli a1, a1, 16
; ZVFH32-NEXT: slli a3, a2, 30
; ZVFH32-NEXT: or a1, a1, a3
; ZVFH32-NEXT: vmv.x.s a3, v9
; ZVFH32-NEXT: slli a2, a2, 17
; ZVFH32-NEXT: slli a3, a3, 16
; ZVFH32-NEXT: srli a2, a2, 19
; ZVFH32-NEXT: srli a3, a3, 1
; ZVFH32-NEXT: or a1, a1, a3
; ZVFH32-NEXT: sw a1, 0(a0)
; ZVFH32-NEXT: sh a4, 4(a0)
; ZVFH32-NEXT: sh a2, 4(a0)
; ZVFH32-NEXT: ret
;
; ZVFH64-LABEL: fp2ui_v3f32_v3i15:
; ZVFH64: # %bb.0:
; ZVFH64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFH64-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFH64-NEXT: lui a1, 16
; ZVFH64-NEXT: vmv.x.s a2, v9
; ZVFH64-NEXT: addiw a1, a1, -1
; ZVFH64-NEXT: vmv.x.s a1, v9
; ZVFH64-NEXT: vslidedown.vi v8, v9, 1
; ZVFH64-NEXT: vslidedown.vi v9, v9, 2
; ZVFH64-NEXT: and a2, a2, a1
; ZVFH64-NEXT: vmv.x.s a3, v8
; ZVFH64-NEXT: and a1, a3, a1
; ZVFH64-NEXT: slli a1, a1, 48
; ZVFH64-NEXT: vmv.x.s a2, v8
; ZVFH64-NEXT: vmv.x.s a3, v9
; ZVFH64-NEXT: srli a1, a1, 48
; ZVFH64-NEXT: slli a2, a2, 48
; ZVFH64-NEXT: slli a3, a3, 30
; ZVFH64-NEXT: slli a1, a1, 15
; ZVFH64-NEXT: or a2, a2, a3
; ZVFH64-NEXT: or a1, a2, a1
; ZVFH64-NEXT: srli a2, a2, 33
; ZVFH64-NEXT: or a1, a1, a3
; ZVFH64-NEXT: or a1, a1, a2
; ZVFH64-NEXT: slli a2, a1, 19
; ZVFH64-NEXT: srli a2, a2, 51
; ZVFH64-NEXT: sw a1, 0(a0)
Expand All @@ -267,42 +261,40 @@ define <3 x i15> @fp2ui_v3f32_v3i15(<3 x float> %x) {
; ZVFHMIN32: # %bb.0:
; ZVFHMIN32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN32-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFHMIN32-NEXT: lui a1, 16
; ZVFHMIN32-NEXT: vslidedown.vi v8, v9, 2
; ZVFHMIN32-NEXT: vmv.x.s a2, v9
; ZVFHMIN32-NEXT: addi a1, a1, -1
; ZVFHMIN32-NEXT: vmv.x.s a1, v9
; ZVFHMIN32-NEXT: vslidedown.vi v9, v9, 1
; ZVFHMIN32-NEXT: vmv.x.s a3, v8
; ZVFHMIN32-NEXT: and a2, a2, a1
; ZVFHMIN32-NEXT: vmv.x.s a4, v9
; ZVFHMIN32-NEXT: and a1, a4, a1
; ZVFHMIN32-NEXT: slli a4, a3, 17
; ZVFHMIN32-NEXT: slli a3, a3, 30
; ZVFHMIN32-NEXT: srli a4, a4, 19
; ZVFHMIN32-NEXT: slli a1, a1, 15
; ZVFHMIN32-NEXT: or a2, a2, a3
; ZVFHMIN32-NEXT: or a1, a2, a1
; ZVFHMIN32-NEXT: vmv.x.s a2, v8
; ZVFHMIN32-NEXT: slli a1, a1, 16
; ZVFHMIN32-NEXT: srli a1, a1, 16
; ZVFHMIN32-NEXT: slli a3, a2, 30
; ZVFHMIN32-NEXT: or a1, a1, a3
; ZVFHMIN32-NEXT: vmv.x.s a3, v9
; ZVFHMIN32-NEXT: slli a2, a2, 17
; ZVFHMIN32-NEXT: slli a3, a3, 16
; ZVFHMIN32-NEXT: srli a2, a2, 19
; ZVFHMIN32-NEXT: srli a3, a3, 1
; ZVFHMIN32-NEXT: or a1, a1, a3
; ZVFHMIN32-NEXT: sw a1, 0(a0)
; ZVFHMIN32-NEXT: sh a4, 4(a0)
; ZVFHMIN32-NEXT: sh a2, 4(a0)
; ZVFHMIN32-NEXT: ret
;
; ZVFHMIN64-LABEL: fp2ui_v3f32_v3i15:
; ZVFHMIN64: # %bb.0:
; ZVFHMIN64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN64-NEXT: vfncvt.rtz.x.f.w v9, v8
; ZVFHMIN64-NEXT: lui a1, 16
; ZVFHMIN64-NEXT: vmv.x.s a2, v9
; ZVFHMIN64-NEXT: addiw a1, a1, -1
; ZVFHMIN64-NEXT: vmv.x.s a1, v9
; ZVFHMIN64-NEXT: vslidedown.vi v8, v9, 1
; ZVFHMIN64-NEXT: vslidedown.vi v9, v9, 2
; ZVFHMIN64-NEXT: and a2, a2, a1
; ZVFHMIN64-NEXT: vmv.x.s a3, v8
; ZVFHMIN64-NEXT: and a1, a3, a1
; ZVFHMIN64-NEXT: slli a1, a1, 48
; ZVFHMIN64-NEXT: vmv.x.s a2, v8
; ZVFHMIN64-NEXT: vmv.x.s a3, v9
; ZVFHMIN64-NEXT: srli a1, a1, 48
; ZVFHMIN64-NEXT: slli a2, a2, 48
; ZVFHMIN64-NEXT: slli a3, a3, 30
; ZVFHMIN64-NEXT: slli a1, a1, 15
; ZVFHMIN64-NEXT: or a2, a2, a3
; ZVFHMIN64-NEXT: or a1, a2, a1
; ZVFHMIN64-NEXT: srli a2, a2, 33
; ZVFHMIN64-NEXT: or a1, a1, a3
; ZVFHMIN64-NEXT: or a1, a1, a2
; ZVFHMIN64-NEXT: slli a2, a1, 19
; ZVFHMIN64-NEXT: srli a2, a2, 51
; ZVFHMIN64-NEXT: sw a1, 0(a0)
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3296,11 +3296,11 @@ define <4 x i16> @buildvec_v4i16_pack(i16 %e1, i16 %e2, i16 %e3, i16 %e4) {
; RVA22U64-LABEL: buildvec_v4i16_pack:
; RVA22U64: # %bb.0:
; RVA22U64-NEXT: slli a3, a3, 48
; RVA22U64-NEXT: zext.h a2, a2
; RVA22U64-NEXT: slli a2, a2, 48
; RVA22U64-NEXT: zext.h a0, a0
; RVA22U64-NEXT: zext.h a1, a1
; RVA22U64-NEXT: slli a2, a2, 32
; RVA22U64-NEXT: slli a1, a1, 16
; RVA22U64-NEXT: slli a1, a1, 48
; RVA22U64-NEXT: srli a2, a2, 16
; RVA22U64-NEXT: srli a1, a1, 32
; RVA22U64-NEXT: or a2, a2, a3
; RVA22U64-NEXT: or a0, a0, a1
; RVA22U64-NEXT: or a0, a0, a2
Expand Down
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