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6 changes: 3 additions & 3 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -5347,9 +5347,9 @@ LegalizerHelper::fewerElementsBitcast(MachineInstr &MI, unsigned int TypeIdx,

auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();

unsigned SrcScalSize = SrcTy.getScalarSizeInBits();
LLT SrcNarrowTy =
LLT::fixed_vector(NarrowTy.getSizeInBits() / SrcScalSize, SrcScalSize);
unsigned NewElemCount =
NarrowTy.getSizeInBits() / SrcTy.getScalarSizeInBits();
LLT SrcNarrowTy = LLT::fixed_vector(NewElemCount, SrcTy.getElementType());
Comment on lines +5350 to +5352
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I think this could use LLT::divide

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LLT::divide operates on element counts not on bit sizes.


// Split the Src and Dst Reg into smaller registers
SmallVector<Register> SrcVRegs, BitcastVRegs;
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3 changes: 1 addition & 2 deletions llvm/lib/CodeGen/GlobalISel/Utils.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -525,8 +525,7 @@ bool llvm::extractParts(Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy,
RegNumElts % LeftoverNumElts == 0 &&
RegTy.getScalarSizeInBits() == MainTy.getScalarSizeInBits() &&
LeftoverNumElts > 1) {
LeftoverTy =
LLT::fixed_vector(LeftoverNumElts, RegTy.getScalarSizeInBits());
LeftoverTy = LLT::fixed_vector(LeftoverNumElts, RegTy.getElementType());

// Unmerge the SrcReg to LeftoverTy vectors
SmallVector<Register, 4> UnmergeValues;
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -154,8 +154,8 @@ static LegalizeMutation moreElementsToNextExistingRegClass(unsigned TypeIdx) {
if (SIRegisterInfo::getSGPRClassForBitWidth(NewNumElts * EltSize))
break;
}

return std::pair(TypeIdx, LLT::fixed_vector(NewNumElts, EltSize));
return std::pair(TypeIdx,
LLT::fixed_vector(NewNumElts, Ty.getElementType()));
};
}

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