[RFC] TableGen-erate SDNode descriptions #119709

s-barannikov · 2024-12-12T14:25:35Z

Landed changes:
#138381 RISCV
#138450 Sparc
#138869 XCore
#138874 ARC, CSKY, Lanai
#138878 MSP430
#139407 AVR
#139449 M68k
#140472 AArch64
#166253 Xtensa
#166259 WebAssembly
#166499 BPF
#168120 VE

topperc · 2024-12-12T16:55:37Z

llvm/include/llvm/CodeGen/SelectionDAGNodes.h

-  /// Test if this node has a target-specific
-  /// memory-referencing opcode (in the \<target\>ISD namespace and
-  /// greater than FIRST_TARGET_MEMORY_OPCODE).
-  bool isTargetMemoryOpcode() const {


Do we still need isTargetMemoryOpcode(). It doesn't have any callers.

It has one use in the assert in SelectionDAG::getMemIntrinsicNode.

Oops. I was looking in my local repo and should have checked for FIRST_TARGET_MEMORY_OPCODE to see that assert

If nothing else is checking it, does that assert provide any value? Can we just allow any target opcode to be a memory opcode?

I remembered it has one more "use". Before this patch it is implicitly checked here. isTargetStrictFPOpcode returns true for memory opcodes as well. mayRaiseFPException is then used here to decide whether the resulting MachineInstr needs NoFPExcept flag. IIUC it will not set this flag on MachineInstrs if the matched SDNode(s) were flagged as memory accessing (or having strict-fp semantics).

This behavior was introduced in 6333679. I couldn't conclude if it is safe to return false for memory opcodes so I left it as is.

After this patch the check is explicit, please see SelectionDAGTargetInfo.cpp:mayRaiseFPException.

I ran CodeGen tests with the memory opcode check disabled and there was one failure in
X86/fp-intrinsics-flags.ll. The following diff resolves it:

There was a discussion in https://reviews.llvm.org/D72466 that can be related to this. Can you confirm that this is a safe change? If so, then quoting @uweigand from https://reviews.llvm.org/D71841 I assume the check for memory opcode can be dropped:

Note that there a bit of a quirk in identifying target nodes that are both memory nodes and strict FP nodes. To simplify the logic, right now all target memory nodes are automatically also considered strict FP nodes -- this could be fixed by adding one more range.

A future patch adds a couple of new methods to this class, which will need to be overridden by these targets. Part of llvm#119709.

…argets (#119968) #119969 adds a couple of new methods to this class, which will need to be overridden by these targets. Part of #119709. Pull Request: #119968

…de (#119969) With this change, targets are no longer required to put memory / strict-fp opcodes after special `ISD::FIRST_TARGET_MEMORY_OPCODE`/`ISD::FIRST_TARGET_STRICTFP_OPCODE` markers. This will also allow autogenerating `isTargetMemoryOpcode`/`isTargetStrictFPOpcode (#119709). Pull Request: #119969

This patch adds a simplistic backend that gathers all target-specific SelectionDAG nodes and emits descriptions for most of them. This includes generating node enumeration, node names, and information about node "prototype" that can be used to verify that a node is valid. The patch also extends SDNode by adding target-specific flags, which are also included in the generated tables. Part of llvm#119709, [RFC](https://discourse.llvm.org/t/rfc-tablegen-erating-sdnode-descriptions/83627).

This patch adds a simplistic backend that gathers all target-specific SelectionDAG nodes and emits descriptions for most of them. This includes generating node enumeration, node names, and information about node "prototype" that can be used to verify that a node is valid. The patch also extends SDNode by adding target-specific flags, which are also included in the generated tables. Part of #119709, [RFC](https://discourse.llvm.org/t/rfc-tablegen-erating-sdnode-descriptions/83627). Pull Request: #123002

This patch introduces SelectionDAGGenTargetInfo and SDNodeInfo classes, which provide methods for accessing the generated SDNode descriptions. RFC: https://discourse.llvm.org/t/rfc-tablegen-erating-sdnode-descriptions Draft PR: llvm#119709

Part of llvm#119709.

This allows SDNodes to be validated against their expected type profiles and reduces the number of changes required to add a new node. CALL and RET_CALL do not have a description in td files, and it is not currently possible to add one as these nodes have both variable operands and variable results. Part of llvm#119709.

This allows SDNodes to be validated against their expected type profiles and reduces the number of changes required to add a new node. CALL and RET_CALL do not have a description in td files, and it is not currently possible to add one as these nodes have both variable operands and variable results. This also fixes a subtle bug detected by the enabled verification functionality. `LOCAL_GET` is declared with `SDNPHasChain` property, and thus should have both a chain operand and a chain result. The original code created a node without a chain result, which caused a check in `SDNodeInfo::verifyNode()` to fail. Part of #119709. Pull Request: #166259

This allows SDNodes to be validated against their expected type profiles and reduces the number of changes required to add a new node. Fix BR_CC/MEMCPY descriptions to match C++ code that creates the nodes. Part of llvm#119709.

This allows SDNodes to be validated against their expected type profiles and reduces the number of changes required to add a new node. Fix BR_CC/MEMCPY descriptions to match C++ code that creates the nodes (an error detected by the enabled verification functionality). Also remove redundant `SDNPOutGlue` on `BPFISD::MEMCPY`. Part of #119709.

This allows SDNodes to be validated against their expected type profiles and reduces the number of changes required to add a new node. Fix BR_CC/MEMCPY descriptions to match C++ code that creates the nodes (an error detected by the enabled verification functionality). Also remove redundant `SDNPOutGlue` on `BPFISD::MEMCPY`. Part of llvm#119709.

Part of llvm#119709.

Part of #119709.

This allows SDNodes to be validated against their expected type profiles and reduces the number of changes required to add a new node. There is a couple of nodes that are missing description and one node that fails validation. Part of #119709. Pull Request: #168120

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s-barannikov marked this pull request as ready for review December 13, 2024 13:37

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This was referenced Dec 14, 2024

[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets #119968

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[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode #119969

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s-barannikov force-pushed the tablegen/sdnode-info-emitter branch from ad38786 to 7ed14ef Compare December 16, 2024 20:32

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s-barannikov mentioned this pull request Jan 15, 2025

[TableGen] Add a backend generating SDNode descriptions #123002

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[X86] Add verifyTargetSDNode for x86 target specific nodes #123589

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s-barannikov force-pushed the tablegen/sdnode-info-emitter branch from 3ba779a to 4c7893b Compare January 22, 2025 06:20

s-barannikov force-pushed the tablegen/sdnode-info-emitter branch from 4c7893b to ae89705 Compare February 1, 2025 19:08

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[SelectionDAG] Wire up -gen-sdnode-info TableGen backend #125358

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s-barannikov added a commit to s-barannikov/llvm-project that referenced this pull request Nov 3, 2025

[Xtensa] TableGen-erate SDNode descriptions

2c15d22

Part of llvm#119709.

s-barannikov mentioned this pull request Nov 3, 2025

[Xtensa] TableGen-erate SDNode descriptions #166253

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s-barannikov mentioned this pull request Nov 3, 2025

[WebAssembly] TableGen-erate SDNode descriptions #166259

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[BPF] TableGen-erate SDNode descriptions #166499

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s-barannikov added a commit to s-barannikov/llvm-project that referenced this pull request Nov 11, 2025

[Xtensa] TableGen-erate SDNode descriptions

f762d97

Part of llvm#119709.

s-barannikov mentioned this pull request Nov 14, 2025

[ARM] Cleanup unused ARMbrcond. NFC #168040

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[Xtensa] TableGen-erate SDNode descriptions (#166253)

05e94c9

Part of #119709.

s-barannikov added 11 commits November 14, 2025 21:44

AMDGPU

913caec

ARM

2ea4f1f

Hexagon

10a6531

LoongArch (ROTL_W, CACOP_D, CACOP_W removed)

85a9681

Mips

01cb4d2

NVPTX

5db8fc3

PowerPC

433b0be

SystemZ

23902c6

VE

e105bb2

X86

fbb7786

Generic bugs

9f09e1f

s-barannikov force-pushed the tablegen/sdnode-info-emitter branch from b0de7ad to 9f09e1f Compare November 14, 2025 18:54

This was referenced Nov 14, 2025

[PowerPC] TableGen-erate SDNode descriptions #168108

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[SystemZ] TableGen-erate node descriptions #168113

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[VE] TableGen-erate SDNode descriptions #168120

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[LoongArch] TableGen-erate SDNode descriptions #168129

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