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[RISCV][VLOPT] Add vector indexed loads and stores to getOperandInfo #119748

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Merged
merged 9 commits into from
Dec 18, 2024
Merged

[RISCV][VLOPT] Add vector indexed loads and stores to getOperandInfo #119748

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8b59858
[RISCV][VLOPT] Add vector indexed instructions to getOperandInfo
michaelmaitland Dec 12, 2024
cf9c153
fixup! add load support
michaelmaitland Dec 12, 2024
d938a67
fixup! improve tests and variable naming
michaelmaitland Dec 17, 2024
9bbb4c2
fixup! fix tests
michaelmaitland Dec 18, 2024
eea71a9
fixup! move vmop_mm back down
michaelmaitland Dec 18, 2024
c775102
fixup! improve test case
michaelmaitland Dec 18, 2024
f695f14
fixup! clean tests
michaelmaitland Dec 18, 2024
1f01333
fixup! name of instr
michaelmaitland Dec 18, 2024
82d5178
fixup! update test checks after rebase
michaelmaitland Dec 18, 2024
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16 changes: 4 additions & 12 deletions llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -635,16 +635,14 @@ body: |
PseudoVSUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */
...
---
name: vluxeiN_v
name: vluxeiN_v_data
body: |
bb.0:
; CHECK-LABEL: name: vluxeiN_v
; CHECK-LABEL: name: vluxeiN_v_data
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
%y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
%z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0
...
---
name: vluxeiN_v_incompatible_eew
Expand All @@ -653,10 +651,8 @@ body: |
; CHECK-LABEL: name: vluxeiN_v_incompatible_eew
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
%y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
%z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0
...
---
name: vluxeiN_v_data_incompatible_emul
Expand All @@ -665,22 +661,18 @@ body: |
; CHECK-LABEL: name: vluxeiN_v_data_incompatible_emul
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: %z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
%y:vr = PseudoVLUXEI8_V_MF2_MF2 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
%z:vr = PseudoVADD_VV_MF2 $noreg, %y, $noreg, 1, 3 /* e8 */, 0
...
---
name: vluxeiN_v_idx_incompatible_emul
name: vluxeiN_v_idx
body: |
bb.0:
; CHECK-LABEL: name: vluxeiN_v_idx_incompatible_emul
; CHECK-LABEL: name: vluxeiN_v_idx
; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: %y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */
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@topperc topperc Dec 18, 2024

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I think this instruction is malformed. One of the M1 needs to be MF2 to match the VADD.

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@topperc topperc Dec 18, 2024 •
edited
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I think the index is first so it should be PseudoVLUXEI8_V_MF2_M1

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@michaelmaitland michaelmaitland Dec 18, 2024

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addressed.

; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
%x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
%y:vr = PseudoVLUXEI8_V_M1_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0
%z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 5 /* e32 */, 0
...
---
name: vmop_mm
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