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merged 5 commits into from
Jan 9, 2025
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[HLSL] Make fast math the default for HLSL #119820

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7a31062
make fast math default for hlsl
spall Dec 12, 2024
b7a9d87
update tests
spall Dec 13, 2024
a3f4c48
Revert "update tests"
spall Dec 18, 2024
795d17e
update broken tests
spall Dec 19, 2024
94d4003
fix failing tests after rebase
spall Jan 8, 2025
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2 changes: 1 addition & 1 deletion clang/include/clang/Driver/Options.td
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Expand Up @@ -2285,7 +2285,7 @@ def ffp_exception_behavior_EQ : Joined<["-"], "ffp-exception-behavior=">, Group<
NormalizedValues<["FPE_Ignore", "FPE_MayTrap", "FPE_Strict"]>,
MarshallingInfoEnum<LangOpts<"FPExceptionMode">, "FPE_Default">;
defm fast_math : BoolFOption<"fast-math",
LangOpts<"FastMath">, DefaultFalse,
LangOpts<"FastMath">, Default<hlsl.KeyPath>,
PosFlag<SetTrue, [], [ClangOption, CC1Option, FC1Option, FlangOption],
"Allow aggressive, lossy floating-point optimizations",
[cl_fast_relaxed_math.KeyPath]>,
Expand Down
4 changes: 2 additions & 2 deletions clang/test/CodeGenHLSL/ArrayTemporary.hlsl
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Expand Up @@ -90,11 +90,11 @@ void template_call(float FA2[2], float FA4[4], int IA3[3]) {

// CHECK: [[Addr:%.*]] = getelementptr inbounds [2 x float], ptr [[FA2]], i32 0, i32 0
// CHECK: [[Tmp:%.*]] = load float, ptr [[Addr]]
// CHECK: call void @_Z11template_fnIfEvT_(float noundef [[Tmp]])
// CHECK: call void @_Z11template_fnIfEvT_(float noundef nofpclass(nan inf) [[Tmp]])

// CHECK: [[Idx0:%.*]] = getelementptr inbounds [2 x float], ptr [[FA2]], i32 0, i32 0
// CHECK: [[Val0:%.*]] = load float, ptr [[Idx0]]
// CHECK: [[Sum:%.*]] = fadd float [[Val0]], 5.000000e+00
// CHECK: [[Sum:%.*]] = fadd reassoc nnan ninf nsz arcp afn float [[Val0]], 5.000000e+00
// CHECK: [[Idx1:%.*]] = getelementptr inbounds [2 x float], ptr [[FA2]], i32 0, i32 1
// CHECK: store float [[Sum]], ptr [[Idx1]]

Expand Down
4 changes: 2 additions & 2 deletions clang/test/CodeGenHLSL/BasicFeatures/OutputArguments.hlsl
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Expand Up @@ -9,7 +9,7 @@
// CHECK: define void {{.*}}trunc_Param{{.*}}(ptr noalias noundef nonnull align 4 dereferenceable(4) {{%.*}})
void trunc_Param(inout int X) {}

// ALL-LABEL: define noundef float {{.*}}case1
// ALL-LABEL: define noundef nofpclass(nan inf) float {{.*}}case1
// CHECK: [[F:%.*]] = alloca float
// CHECK: [[ArgTmp:%.*]] = alloca i32
// CHECK: [[FVal:%.*]] = load float, ptr {{.*}}
Expand Down Expand Up @@ -197,7 +197,7 @@ export int case7() {
// CHECK: define void {{.*}}trunc_vec{{.*}}(ptr noalias noundef nonnull align 16 dereferenceable(16) {{%.*}})
void trunc_vec(inout int3 V) {}

// ALL-LABEL: define noundef <3 x float> {{.*}}case8
// ALL-LABEL: define noundef nofpclass(nan inf) <3 x float> {{.*}}case8

// CHECK: [[V:%.*]] = alloca <3 x float>
// CHECK: [[Tmp:%.*]] = alloca <3 x i32>
Expand Down
6 changes: 3 additions & 3 deletions clang/test/CodeGenHLSL/BasicFeatures/standard_conversion_sequences.hlsl
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Expand Up @@ -6,7 +6,7 @@
// CHECK: store <3 x float> splat (float 1.000000e+00), ptr [[f3]]
// CHECK: [[vecf3:%.*]] = load <3 x float>, ptr [[f3]]
// CHECK: [[vecf4:%.*]] = shufflevector <3 x float> [[vecf3]], <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 0>
// CHECK: [[vecd4:%.*]] = fpext <4 x float> [[vecf4]] to <4 x double>
// CHECK: [[vecd4:%.*]] = fpext reassoc nnan ninf nsz arcp afn <4 x float> [[vecf4]] to <4 x double>
// CHECK: store <4 x double> [[vecd4]], ptr [[d4]]
void f3_to_d4() {
vector<float,3> f3 = 1.0;
Expand All @@ -30,7 +30,7 @@ void f3_to_f2() {
// CHECK: [[f2:%.*]] = alloca <2 x float>
// CHECK: store <4 x double> splat (double 3.000000e+00), ptr [[d4]]
// CHECK: [[vecd4:%.*]] = load <4 x double>, ptr [[d4]]
// CHECK: [[vecf4:%.*]] = fptrunc <4 x double> [[vecd4]] to <4 x float>
// CHECK: [[vecf4:%.*]] = fptrunc reassoc nnan ninf nsz arcp afn <4 x double> [[vecd4]] to <4 x float>
// CHECK: [[vecf2:%.*]] = shufflevector <4 x float> [[vecf4]], <4 x float> poison, <2 x i32> <i32 0, i32 1>
// CHECK: store <2 x float> [[vecf2]], ptr [[f2]]
void d4_to_f2() {
Expand Down Expand Up @@ -108,7 +108,7 @@ void i2_to_b2() {
// CHECK: [[b2:%.*]] = alloca i8
// CHECK: store <4 x double> splat (double 9.000000e+00), ptr [[d4]]
// CHECK: [[vecd4:%.*]] = load <4 x double>, ptr [[d4]]
// CHECK: [[vecb4:%.*]] = fcmp une <4 x double> [[vecd4]], zeroinitializer
// CHECK: [[vecb4:%.*]] = fcmp reassoc nnan ninf nsz arcp afn une <4 x double> [[vecd4]], zeroinitializer
// CHECK: [[vecd2:%.*]] = shufflevector <4 x i1> [[vecb4]], <4 x i1> poison, <2 x i32> <i32 0, i32 1>
// CHECK: [[vecb8:%.*]] = shufflevector <2 x i1> [[vecd2]], <2 x i1> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
// CHECK: [[i8:%.*]] = bitcast <8 x i1> [[vecb8]] to i8
Expand Down
2 changes: 1 addition & 1 deletion clang/test/CodeGenHLSL/builtins/ScalarSwizzles.hlsl
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Expand Up @@ -119,7 +119,7 @@ float2 HowManyFloats(float V) {
// CHECK: store <1 x double> splat (double 1.000000e+00), ptr [[Tmp]], align 8
// CHECK: [[vec1:%.*]] = load <1 x double>, ptr [[Tmp]], align 8
// CHECK: [[vec3:%.*]] = shufflevector <1 x double> [[vec1]], <1 x double> poison, <3 x i32> zeroinitializer
// CHECK: [[vec3f:%.*]] = fptrunc <3 x double> [[vec3]] to <3 x float>
// CHECK: [[vec3f:%.*]] = fptrunc reassoc nnan ninf nsz arcp afn <3 x double> [[vec3]] to <3 x float>
// CHECK: ret <3 x float> [[vec3f]]

float3 AllRighty() {
Expand Down
6 changes: 3 additions & 3 deletions clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-lib.hlsl
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Expand Up @@ -33,7 +33,7 @@ export void TestAppend(float value) {
ASB.Append(value);
}

// CHECK: define void @_Z10TestAppendf(float noundef %value)
// CHECK: define void @_Z10TestAppendf(float noundef nofpclass(nan inf) %value)
// CHECK-DXIL: %[[VALUE:.*]] = load float, ptr %value.addr, align 4
// CHECK-DXIL: %[[INDEX:.*]] = call i32 @llvm.dx.resource.updatecounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %{{[0-9]+}}, i8 1)
// CHECK-DXIL: %[[RESPTR:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %{{[0-9]+}}, i32 %[[INDEX]])
Expand All @@ -43,7 +43,7 @@ export float TestConsume() {
return CSB.Consume();
}

// CHECK: define noundef float @_Z11TestConsumev()
// CHECK: define noundef nofpclass(nan inf) float @_Z11TestConsumev()
// CHECK-DXIL: %[[INDEX:.*]] = call i32 @llvm.dx.resource.updatecounter.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %1, i8 -1)
// CHECK-DXIL: %[[RESPTR:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %0, i32 %[[INDEX]])
// CHECK-DXIL: %[[VALUE:.*]] = load float, ptr %[[RESPTR]], align 4
Expand All @@ -53,7 +53,7 @@ export float TestLoad() {
return RWSB1.Load(1) + SB1.Load(2);
}

// CHECK: define noundef float @_Z8TestLoadv()
// CHECK: define noundef nofpclass(nan inf) float @_Z8TestLoadv()
// CHECK: %[[PTR1:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_f32_1_0t(target("dx.RawBuffer", float, 1, 0) %{{[0-9]+}}, i32 %{{[0-9]+}})
// CHECK: %[[VALUE1:.*]] = load float, ptr %[[PTR1]]
// CHECK: %[[PTR2:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_f32_0_0t(target("dx.RawBuffer", float, 0, 0) %{{[0-9]+}}, i32 %{{[0-9]+}})
Expand Down
2 changes: 1 addition & 1 deletion clang/test/CodeGenHLSL/builtins/StructuredBuffers-methods-ps.hlsl
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Expand Up @@ -28,7 +28,7 @@ export float TestLoad() {
return ROSB1.Load(10);
}

// CHECK: define noundef float @_Z8TestLoadv()
// CHECK: define noundef nofpclass(nan inf) float @_Z8TestLoadv()
// CHECK: %[[PTR1:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_f32_1_1t(target("dx.RawBuffer", float, 1, 1) %{{[0-9]+}}, i32 %{{[0-9]+}})
// CHECK: %[[VALUE1:.*]] = load float, ptr %[[PTR1]]

Expand Down
12 changes: 6 additions & 6 deletions clang/test/CodeGenHLSL/builtins/WaveReadLaneAt.hlsl
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Expand Up @@ -38,8 +38,8 @@ int16_t test_int16(int16_t expr, uint idx) {
// CHECK-LABEL: test_half
half test_half(half expr, uint idx) {
// CHECK-SPIRV: %[[#entry_tok2:]] = call token @llvm.experimental.convergence.entry()
// CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.readlane.f16([[TY]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok2]]) ]
// CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.readlane.f16([[TY]] %[[#]], i32 %[[#]])
// CHECK-SPIRV: %[[RET:.*]] = call reassoc nnan ninf nsz arcp afn spir_func [[TY:.*]] @llvm.spv.wave.readlane.f16([[TY]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok2]]) ]
// CHECK-DXIL: %[[RET:.*]] = call reassoc nnan ninf nsz arcp afn [[TY:.*]] @llvm.dx.wave.readlane.f16([[TY]] %[[#]], i32 %[[#]])
// CHECK: ret [[TY]] %[[RET]]
return WaveReadLaneAt(expr, idx);
}
Expand All @@ -50,8 +50,8 @@ half test_half(half expr, uint idx) {
// CHECK-LABEL: test_double
double test_double(double expr, uint idx) {
// CHECK-SPIRV: %[[#entry_tok3:]] = call token @llvm.experimental.convergence.entry()
// CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.readlane.f64([[TY]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok3]]) ]
// CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.readlane.f64([[TY]] %[[#]], i32 %[[#]])
// CHECK-SPIRV: %[[RET:.*]] = call reassoc nnan ninf nsz arcp afn spir_func [[TY:.*]] @llvm.spv.wave.readlane.f64([[TY]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok3]]) ]
// CHECK-DXIL: %[[RET:.*]] = call reassoc nnan ninf nsz arcp afn [[TY:.*]] @llvm.dx.wave.readlane.f64([[TY]] %[[#]], i32 %[[#]])
// CHECK: ret [[TY]] %[[RET]]
return WaveReadLaneAt(expr, idx);
}
Expand All @@ -62,8 +62,8 @@ double test_double(double expr, uint idx) {
// CHECK-LABEL: test_floatv4
float4 test_floatv4(float4 expr, uint idx) {
// CHECK-SPIRV: %[[#entry_tok4:]] = call token @llvm.experimental.convergence.entry()
// CHECK-SPIRV: %[[RET1:.*]] = call spir_func [[TY1:.*]] @llvm.spv.wave.readlane.v4f32([[TY1]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok4]]) ]
// CHECK-DXIL: %[[RET1:.*]] = call [[TY1:.*]] @llvm.dx.wave.readlane.v4f32([[TY1]] %[[#]], i32 %[[#]])
// CHECK-SPIRV: %[[RET1:.*]] = call reassoc nnan ninf nsz arcp afn spir_func [[TY1:.*]] @llvm.spv.wave.readlane.v4f32([[TY1]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok4]]) ]
// CHECK-DXIL: %[[RET1:.*]] = call reassoc nnan ninf nsz arcp afn [[TY1:.*]] @llvm.dx.wave.readlane.v4f32([[TY1]] %[[#]], i32 %[[#]])
// CHECK: ret [[TY1]] %[[RET1]]
return WaveReadLaneAt(expr, idx);
}
Expand Down
64 changes: 32 additions & 32 deletions clang/test/CodeGenHLSL/builtins/abs.hlsl
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Expand Up @@ -22,25 +22,25 @@ int16_t3 test_abs_int16_t3(int16_t3 p0) { return abs(p0); }
int16_t4 test_abs_int16_t4(int16_t4 p0) { return abs(p0); }
#endif // __HLSL_ENABLE_16_BIT

// NATIVE_HALF-LABEL: define noundef half @_Z13test_abs_half
// NATIVE_HALF: call half @llvm.fabs.f16(
// NO_HALF-LABEL: define noundef float @_Z13test_abs_half
// NO_HALF: call float @llvm.fabs.f32(float %0)
// NATIVE_HALF-LABEL: define noundef nofpclass(nan inf) half @_Z13test_abs_half
// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn half @llvm.fabs.f16(
// NO_HALF-LABEL: define noundef nofpclass(nan inf) float @_Z13test_abs_half
// NO_HALF: call reassoc nnan ninf nsz arcp afn float @llvm.fabs.f32(float %0)
half test_abs_half(half p0) { return abs(p0); }
// NATIVE_HALF-LABEL: define noundef <2 x half> @_Z14test_abs_half2
// NATIVE_HALF: call <2 x half> @llvm.fabs.v2f16(
// NO_HALF-LABEL: define noundef <2 x float> @_Z14test_abs_half2
// NO_HALF: call <2 x float> @llvm.fabs.v2f32(
// NATIVE_HALF-LABEL: define noundef nofpclass(nan inf) <2 x half> @_Z14test_abs_half2
// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn <2 x half> @llvm.fabs.v2f16(
// NO_HALF-LABEL: define noundef nofpclass(nan inf) <2 x float> @_Z14test_abs_half2
// NO_HALF: call reassoc nnan ninf nsz arcp afn <2 x float> @llvm.fabs.v2f32(
half2 test_abs_half2(half2 p0) { return abs(p0); }
// NATIVE_HALF-LABEL: define noundef <3 x half> @_Z14test_abs_half3
// NATIVE_HALF: call <3 x half> @llvm.fabs.v3f16(
// NO_HALF-LABEL: define noundef <3 x float> @_Z14test_abs_half3
// NO_HALF: call <3 x float> @llvm.fabs.v3f32(
// NATIVE_HALF-LABEL: define noundef nofpclass(nan inf) <3 x half> @_Z14test_abs_half3
// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn <3 x half> @llvm.fabs.v3f16(
// NO_HALF-LABEL: define noundef nofpclass(nan inf) <3 x float> @_Z14test_abs_half3
// NO_HALF: call reassoc nnan ninf nsz arcp afn <3 x float> @llvm.fabs.v3f32(
half3 test_abs_half3(half3 p0) { return abs(p0); }
// NATIVE_HALF-LABEL: define noundef <4 x half> @_Z14test_abs_half4
// NATIVE_HALF: call <4 x half> @llvm.fabs.v4f16(
// NO_HALF-LABEL: define noundef <4 x float> @_Z14test_abs_half4
// NO_HALF: call <4 x float> @llvm.fabs.v4f32(
// NATIVE_HALF-LABEL: define noundef nofpclass(nan inf) <4 x half> @_Z14test_abs_half4
// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn <4 x half> @llvm.fabs.v4f16(
// NO_HALF-LABEL: define noundef nofpclass(nan inf) <4 x float> @_Z14test_abs_half4
// NO_HALF: call reassoc nnan ninf nsz arcp afn <4 x float> @llvm.fabs.v4f32(
half4 test_abs_half4(half4 p0) { return abs(p0); }

// CHECK-LABEL: define noundef i32 @_Z12test_abs_int
Expand All @@ -56,17 +56,17 @@ int3 test_abs_int3(int3 p0) { return abs(p0); }
// CHECK: call <4 x i32> @llvm.abs.v4i32(
int4 test_abs_int4(int4 p0) { return abs(p0); }

// CHECK-LABEL: define noundef float @_Z14test_abs_float
// CHECK: call float @llvm.fabs.f32(
// CHECK-LABEL: define noundef nofpclass(nan inf) float @_Z14test_abs_float
// CHECK: call reassoc nnan ninf nsz arcp afn float @llvm.fabs.f32(
float test_abs_float(float p0) { return abs(p0); }
// CHECK-LABEL: define noundef <2 x float> @_Z15test_abs_float2
// CHECK: call <2 x float> @llvm.fabs.v2f32(
// CHECK-LABEL: define noundef nofpclass(nan inf) <2 x float> @_Z15test_abs_float2
// CHECK: call reassoc nnan ninf nsz arcp afn <2 x float> @llvm.fabs.v2f32(
float2 test_abs_float2(float2 p0) { return abs(p0); }
// CHECK-LABEL: define noundef <3 x float> @_Z15test_abs_float3
// CHECK: call <3 x float> @llvm.fabs.v3f32(
// CHECK-LABEL: define noundef nofpclass(nan inf) <3 x float> @_Z15test_abs_float3
// CHECK: call reassoc nnan ninf nsz arcp afn <3 x float> @llvm.fabs.v3f32(
float3 test_abs_float3(float3 p0) { return abs(p0); }
// CHECK-LABEL: define noundef <4 x float> @_Z15test_abs_float4
// CHECK: call <4 x float> @llvm.fabs.v4f32(
// CHECK-LABEL: define noundef nofpclass(nan inf) <4 x float> @_Z15test_abs_float4
// CHECK: call reassoc nnan ninf nsz arcp afn <4 x float> @llvm.fabs.v4f32(
float4 test_abs_float4(float4 p0) { return abs(p0); }

// CHECK-LABEL: define noundef i64 @_Z16test_abs_int64_t
Expand All @@ -82,15 +82,15 @@ int64_t3 test_abs_int64_t3(int64_t3 p0) { return abs(p0); }
// CHECK: call <4 x i64> @llvm.abs.v4i64(
int64_t4 test_abs_int64_t4(int64_t4 p0) { return abs(p0); }

// CHECK-LABEL: define noundef double @_Z15test_abs_double
// CHECK: call double @llvm.fabs.f64(
// CHECK-LABEL: define noundef nofpclass(nan inf) double @_Z15test_abs_double
// CHECK: call reassoc nnan ninf nsz arcp afn double @llvm.fabs.f64(
double test_abs_double(double p0) { return abs(p0); }
// CHECK-LABEL: define noundef <2 x double> @_Z16test_abs_double2
// CHECK: call <2 x double> @llvm.fabs.v2f64(
// CHECK-LABEL: define noundef nofpclass(nan inf) <2 x double> @_Z16test_abs_double2
// CHECK: call reassoc nnan ninf nsz arcp afn <2 x double> @llvm.fabs.v2f64(
double2 test_abs_double2(double2 p0) { return abs(p0); }
// CHECK-LABEL: define noundef <3 x double> @_Z16test_abs_double3
// CHECK: call <3 x double> @llvm.fabs.v3f64(
// CHECK-LABEL: define noundef nofpclass(nan inf) <3 x double> @_Z16test_abs_double3
// CHECK: call reassoc nnan ninf nsz arcp afn <3 x double> @llvm.fabs.v3f64(
double3 test_abs_double3(double3 p0) { return abs(p0); }
// CHECK-LABEL: define noundef <4 x double> @_Z16test_abs_double4
// CHECK: call <4 x double> @llvm.fabs.v4f64(
// CHECK-LABEL: define noundef nofpclass(nan inf) <4 x double> @_Z16test_abs_double4
// CHECK: call reassoc nnan ninf nsz arcp afn <4 x double> @llvm.fabs.v4f64(
double4 test_abs_double4(double4 p0) { return abs(p0); }
24 changes: 12 additions & 12 deletions clang/test/CodeGenHLSL/builtins/acos.hlsl
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Expand Up @@ -7,53 +7,53 @@
// RUN: -o - | FileCheck %s --check-prefixes=CHECK,NO_HALF

// CHECK-LABEL: test_acos_half
// NATIVE_HALF: call half @llvm.acos.f16
// NO_HALF: call float @llvm.acos.f32
// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn half @llvm.acos.f16
// NO_HALF: call reassoc nnan ninf nsz arcp afn float @llvm.acos.f32
half test_acos_half ( half p0 ) {
return acos ( p0 );
}

// CHECK-LABEL: test_acos_half2
// NATIVE_HALF: call <2 x half> @llvm.acos.v2f16
// NO_HALF: call <2 x float> @llvm.acos.v2f32
// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn <2 x half> @llvm.acos.v2f16
// NO_HALF: call reassoc nnan ninf nsz arcp afn <2 x float> @llvm.acos.v2f32
half2 test_acos_half2 ( half2 p0 ) {
return acos ( p0 );
}

// CHECK-LABEL: test_acos_half3
// NATIVE_HALF: call <3 x half> @llvm.acos.v3f16
// NO_HALF: call <3 x float> @llvm.acos.v3f32
// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn <3 x half> @llvm.acos.v3f16
// NO_HALF: call reassoc nnan ninf nsz arcp afn <3 x float> @llvm.acos.v3f32
half3 test_acos_half3 ( half3 p0 ) {
return acos ( p0 );
}

// CHECK-LABEL: test_acos_half4
// NATIVE_HALF: call <4 x half> @llvm.acos.v4f16
// NO_HALF: call <4 x float> @llvm.acos.v4f32
// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn <4 x half> @llvm.acos.v4f16
// NO_HALF: call reassoc nnan ninf nsz arcp afn <4 x float> @llvm.acos.v4f32
half4 test_acos_half4 ( half4 p0 ) {
return acos ( p0 );
}

// CHECK-LABEL: test_acos_float
// CHECK: call float @llvm.acos.f32
// CHECK: call reassoc nnan ninf nsz arcp afn float @llvm.acos.f32
float test_acos_float ( float p0 ) {
return acos ( p0 );
}

// CHECK-LABEL: test_acos_float2
// CHECK: call <2 x float> @llvm.acos.v2f32
// CHECK: call reassoc nnan ninf nsz arcp afn <2 x float> @llvm.acos.v2f32
float2 test_acos_float2 ( float2 p0 ) {
return acos ( p0 );
}

// CHECK-LABEL: test_acos_float3
// CHECK: call <3 x float> @llvm.acos.v3f32
// CHECK: call reassoc nnan ninf nsz arcp afn <3 x float> @llvm.acos.v3f32
float3 test_acos_float3 ( float3 p0 ) {
return acos ( p0 );
}

// CHECK-LABEL: test_acos_float4
// CHECK: call <4 x float> @llvm.acos.v4f32
// CHECK: call reassoc nnan ninf nsz arcp afn <4 x float> @llvm.acos.v4f32
float4 test_acos_float4 ( float4 p0 ) {
return acos ( p0 );
}
4 changes: 2 additions & 2 deletions clang/test/CodeGenHLSL/builtins/asdouble.hlsl
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ double test_uint(uint low, uint high) {
// CHECK-SPV-SAME: {{.*}} <i32 0, i32 1>
// CHECK-SPV: bitcast <2 x i32> %[[SHUFFLE0]] to double

// CHECK-DXIL: call double @llvm.dx.asdouble.i32
// CHECK-DXIL: call reassoc nnan ninf nsz arcp afn double @llvm.dx.asdouble.i32
return asdouble(low, high);
}

Expand All @@ -30,7 +30,7 @@ double3 test_vuint(uint3 low, uint3 high) {
// CHECK-SPV-SAME: {{.*}} <i32 0, i32 3, i32 1, i32 4, i32 2, i32 5>
// CHECK-SPV: bitcast <6 x i32> %[[SHUFFLE1]] to <3 x double>

// CHECK-DXIL: call <3 x double> @llvm.dx.asdouble.v3i32
// CHECK-DXIL: call reassoc nnan ninf nsz arcp afn <3 x double> @llvm.dx.asdouble.v3i32
return asdouble(low, high);
}

Expand Down
24 changes: 12 additions & 12 deletions clang/test/CodeGenHLSL/builtins/asin.hlsl
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Original file line number Diff line number Diff line change
Expand Up @@ -7,53 +7,53 @@
// RUN: -o - | FileCheck %s --check-prefixes=CHECK,NO_HALF

// CHECK-LABEL: test_asin_half
// NATIVE_HALF: call half @llvm.asin.f16
// NO_HALF: call float @llvm.asin.f32
// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn half @llvm.asin.f16
// NO_HALF: call reassoc nnan ninf nsz arcp afn float @llvm.asin.f32
half test_asin_half ( half p0 ) {
return asin ( p0 );
}

// CHECK-LABEL: test_asin_half2
// NATIVE_HALF: call <2 x half> @llvm.asin.v2f16
// NO_HALF: call <2 x float> @llvm.asin.v2f32
// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn <2 x half> @llvm.asin.v2f16
// NO_HALF: call reassoc nnan ninf nsz arcp afn <2 x float> @llvm.asin.v2f32
half2 test_asin_half2 ( half2 p0 ) {
return asin ( p0 );
}

// CHECK-LABEL: test_asin_half3
// NATIVE_HALF: call <3 x half> @llvm.asin.v3f16
// NO_HALF: call <3 x float> @llvm.asin.v3f32
// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn <3 x half> @llvm.asin.v3f16
// NO_HALF: call reassoc nnan ninf nsz arcp afn <3 x float> @llvm.asin.v3f32
half3 test_asin_half3 ( half3 p0 ) {
return asin ( p0 );
}

// CHECK-LABEL: test_asin_half4
// NATIVE_HALF: call <4 x half> @llvm.asin.v4f16
// NO_HALF: call <4 x float> @llvm.asin.v4f32
// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn <4 x half> @llvm.asin.v4f16
// NO_HALF: call reassoc nnan ninf nsz arcp afn <4 x float> @llvm.asin.v4f32
half4 test_asin_half4 ( half4 p0 ) {
return asin ( p0 );
}

// CHECK-LABEL: test_asin_float
// CHECK: call float @llvm.asin.f32
// CHECK: call reassoc nnan ninf nsz arcp afn float @llvm.asin.f32
float test_asin_float ( float p0 ) {
return asin ( p0 );
}

// CHECK-LABEL: test_asin_float2
// CHECK: call <2 x float> @llvm.asin.v2f32
// CHECK: call reassoc nnan ninf nsz arcp afn <2 x float> @llvm.asin.v2f32
float2 test_asin_float2 ( float2 p0 ) {
return asin ( p0 );
}

// CHECK-LABEL: test_asin_float3
// CHECK: call <3 x float> @llvm.asin.v3f32
// CHECK: call reassoc nnan ninf nsz arcp afn <3 x float> @llvm.asin.v3f32
float3 test_asin_float3 ( float3 p0 ) {
return asin ( p0 );
}

// CHECK-LABEL: test_asin_float4
// CHECK: call <4 x float> @llvm.asin.v4f32
// CHECK: call reassoc nnan ninf nsz arcp afn <4 x float> @llvm.asin.v4f32
float4 test_asin_float4 ( float4 p0 ) {
return asin ( p0 );
}
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