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[TargetLibraryInfo] Add libmvec support for risc-v #119844

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101d7cb
[NFC] Add vector call tests if use vector-library in risc-v
zengdage Dec 12, 2024
023a029
[TargetLibraryInfo] Add libmvec support for risc-v
zengdage Dec 13, 2024
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6 changes: 4 additions & 2 deletions clang/lib/Driver/ToolChains/Clang.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5805,9 +5805,11 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
Triple.getArch() != llvm::Triple::x86_64)
D.Diag(diag::err_drv_unsupported_opt_for_target)
<< Name << Triple.getArchName();
} else if (Name == "LIBMVEC-X86") {
} else if (Name == "LIBMVEC") {
if (Triple.getArch() != llvm::Triple::x86 &&
Triple.getArch() != llvm::Triple::x86_64)
Triple.getArch() != llvm::Triple::x86_64 &&
Triple.getArch() != llvm::Triple::riscv32 &&
Triple.getArch() != llvm::Triple::riscv64)
D.Diag(diag::err_drv_unsupported_opt_for_target)
<< Name << Triple.getArchName();
} else if (Name == "SLEEF" || Name == "ArmPL") {
Expand Down
2 changes: 1 addition & 1 deletion clang/lib/Driver/ToolChains/CommonArgs.cpp
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Expand Up @@ -909,7 +909,7 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const ArgList &Args,
std::optional<StringRef> OptVal =
llvm::StringSwitch<std::optional<StringRef>>(ArgVecLib->getValue())
.Case("Accelerate", "Accelerate")
.Case("LIBMVEC", "LIBMVEC-X86")
.Case("LIBMVEC", "LIBMVEC")
.Case("MASSV", "MASSV")
.Case("SVML", "SVML")
.Case("SLEEF", "sleefgnuabi")
Expand Down
6 changes: 4 additions & 2 deletions clang/lib/Driver/ToolChains/Flang.cpp
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Expand Up @@ -446,9 +446,11 @@ void Flang::addTargetOptions(const ArgList &Args,
Triple.getArch() != llvm::Triple::x86_64)
D.Diag(diag::err_drv_unsupported_opt_for_target)
<< Name << Triple.getArchName();
} else if (Name == "LIBMVEC-X86") {
} else if (Name == "LIBMVEC") {
if (Triple.getArch() != llvm::Triple::x86 &&
Triple.getArch() != llvm::Triple::x86_64)
Triple.getArch() != llvm::Triple::x86_64 &&
Triple.getArch() != llvm::Triple::riscv32 &&
Triple.getArch() != llvm::Triple::riscv64)
D.Diag(diag::err_drv_unsupported_opt_for_target)
<< Name << Triple.getArchName();
} else if (Name == "SLEEF" || Name == "ArmPL") {
Expand Down
10 changes: 7 additions & 3 deletions clang/test/Driver/fveclib.c
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Expand Up @@ -5,6 +5,7 @@
// RUN: %clang -### -c -fveclib=Darwin_libsystem_m %s 2>&1 | FileCheck --check-prefix=CHECK-DARWIN_LIBSYSTEM_M %s
// RUN: %clang -### -c --target=aarch64 -fveclib=SLEEF %s 2>&1 | FileCheck --check-prefix=CHECK-SLEEF %s
// RUN: %clang -### -c --target=riscv64-unknown-linux-gnu -fveclib=SLEEF -march=rv64gcv %s 2>&1 | FileCheck -check-prefix CHECK-SLEEF-RISCV %s
// RUN: %clang -### -c --target=riscv64-unknown-linux-gnu -fveclib=libmvec -march=rv64gcv %s 2>&1 | FileCheck -check-prefix CHECK-libmvec %s
// RUN: %clang -### -c --target=aarch64 -fveclib=ArmPL %s 2>&1 | FileCheck --check-prefix=CHECK-ARMPL %s
// RUN: not %clang -c -fveclib=something %s 2>&1 | FileCheck --check-prefix=CHECK-INVALID %s

Expand All @@ -21,7 +22,7 @@

// RUN: not %clang --target=x86 -c -fveclib=SLEEF %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
// RUN: not %clang --target=x86 -c -fveclib=ArmPL %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
// RUN: not %clang --target=aarch64 -c -fveclib=LIBMVEC-X86 %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
// RUN: not %clang --target=aarch64 -c -fveclib=LIBMVEC %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
// RUN: not %clang --target=aarch64 -c -fveclib=SVML %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
// CHECK-ERROR: unsupported option {{.*}} for target

Expand All @@ -38,7 +39,7 @@
/* Verify that the correct vector library is passed to LTO flags. */

// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fveclib=LIBMVEC -flto %s 2>&1 | FileCheck --check-prefix=CHECK-LTO-LIBMVEC %s
// CHECK-LTO-LIBMVEC: "-plugin-opt=-vector-library=LIBMVEC-X86"
// CHECK-LTO-LIBMVEC: "-plugin-opt=-vector-library=LIBMVEC"

// RUN: %clang -### --target=powerpc64-unknown-linux-gnu -fveclib=MASSV -flto %s 2>&1 | FileCheck --check-prefix=CHECK-LTO-MASSV %s
// CHECK-LTO-MASSV: "-plugin-opt=-vector-library=MASSV"
Expand All @@ -52,6 +53,9 @@
// RUN: %clang -### --target=riscv64-unknown-linux-gnu -fveclib=SLEEF -flto -march=rv64gcv %s 2>&1 | FileCheck -check-prefix CHECK-LTO-SLEEF-RISCV %s
// CHECK-LTO-SLEEF-RISCV: "-plugin-opt=-vector-library=sleefgnuabi"

// RUN: %clang -### --target=riscv64-unknown-linux-gnu -fveclib=LIBMVEC -flto -march=rv64gcv %s 2>&1 | FileCheck -check-prefix CHECK-LTO-LIBMVEC-RISCV %s
// CHECK-LTO-LIBMVEC-RISCV: "-plugin-opt=-vector-library=LIBMVEC"

// RUN: %clang -### --target=aarch64-linux-gnu -fveclib=ArmPL -flto %s 2>&1 | FileCheck --check-prefix=CHECK-LTO-ARMPL %s
// CHECK-LTO-ARMPL: "-plugin-opt=-vector-library=ArmPL"

Expand Down Expand Up @@ -110,7 +114,7 @@
// CHECK-ENABLED-LAST: math errno enabled by '-ffp-model=strict' after it was implicitly disabled by '-fveclib=ArmPL', this may limit the utilization of the vector library [-Wmath-errno-enabled-with-veclib]

/* Verify no warning when math-errno is re-enabled for a different veclib (that does not imply -fno-math-errno). */
// RUN: %clang -### --target=aarch64-linux-gnu -fveclib=ArmPL -fmath-errno -fveclib=LIBMVEC %s 2>&1 | FileCheck --check-prefix=CHECK-REPEAT-VECLIB %s
// RUN: %clang -### --target=aarch64-linux-gnu -fveclib=ArmPL -fmath-errno -fveclib=LIBMVEC-X86 %s 2>&1 | FileCheck --check-prefix=CHECK-REPEAT-VECLIB %s
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@mag-mga mag-mga Dec 20, 2024

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Why did you leave x86 for arm here?

// CHECK-REPEAT-VECLIB-NOT: math errno enabled

/// Verify that vectorized routines library is being linked in.
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2 changes: 1 addition & 1 deletion llvm/include/llvm/Analysis/TargetLibraryInfo.h
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Expand Up @@ -124,7 +124,7 @@ class TargetLibraryInfoImpl {
NoLibrary, // Don't use any vector library.
Accelerate, // Use Accelerate framework.
DarwinLibSystemM, // Use Darwin's libsystem_m.
LIBMVEC_X86, // GLIBC Vector Math library.
LIBMVEC, // GLIBC Vector Math library.
MASSV, // IBM MASS vector library.
SVML, // Intel short vector math library.
SLEEFGNUABI, // SLEEF - SIMD Library for Evaluating Elementary Functions.
Expand Down
73 changes: 73 additions & 0 deletions llvm/include/llvm/Analysis/VecFuncs.def
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Expand Up @@ -236,6 +236,79 @@ TLI_DEFINE_VECFUNC("llvm.log.f64", "_ZGVdN4v_log", FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVbN4v_logf", FIXED(4), "_ZGV_LLVM_N4v")
TLI_DEFINE_VECFUNC("llvm.log.f32", "_ZGVdN8v_logf", FIXED(8), "_ZGV_LLVM_N8v")

#elif defined(TLI_DEFINE_LIBMVEC_RVV_VECFUNCS)
// GLIBC Vector math Functions for RISC-V

TLI_DEFINE_VECFUNC("sin", "_ZGV1Nxv_sin", SCALABLE(1), "_ZGVr1Nxv")
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@mag-mga mag-mga Dec 20, 2024

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You have missed r letter in mangled vector name`after ZGV according to mention MR

TLI_DEFINE_VECFUNC("sin", "_ZGV2Nxv_sin", SCALABLE(2), "_ZGVr2Nxv")
TLI_DEFINE_VECFUNC("sin", "_ZGV4Nxv_sin", SCALABLE(4), "_ZGVr4Nxv")
TLI_DEFINE_VECFUNC("sin", "_ZGV8Nxv_sin", SCALABLE(8), "_ZGVr8Nxv")

TLI_DEFINE_VECFUNC("llvm.sin.f64", "_ZGV1Nxv_sin", SCALABLE(1), "_ZGVr1Nxv")
TLI_DEFINE_VECFUNC("llvm.sin.f64", "_ZGV2Nxv_sin", SCALABLE(2), "_ZGVr2Nxv")
TLI_DEFINE_VECFUNC("llvm.sin.f64", "_ZGV4Nxv_sin", SCALABLE(4), "_ZGVr4Nxv")
TLI_DEFINE_VECFUNC("llvm.sin.f64", "_ZGV8Nxv_sin", SCALABLE(8), "_ZGVr8Nxv")

TLI_DEFINE_VECFUNC("cos", "_ZGV1Nxv_cos", SCALABLE(1), "_ZGVr1Nxv")
TLI_DEFINE_VECFUNC("cos", "_ZGV2Nxv_cos", SCALABLE(2), "_ZGVr2Nxv")
TLI_DEFINE_VECFUNC("cos", "_ZGV4Nxv_cos", SCALABLE(4), "_ZGVr4Nxv")
TLI_DEFINE_VECFUNC("cos", "_ZGV8Nxv_cos", SCALABLE(8), "_ZGVr8Nxv")

TLI_DEFINE_VECFUNC("llvm.cos.f64", "_ZGV1Nxv_cos", SCALABLE(1), "_ZGVr1Nxv")
TLI_DEFINE_VECFUNC("llvm.cos.f64", "_ZGV2Nxv_cos", SCALABLE(2), "_ZGVr2Nxv")
TLI_DEFINE_VECFUNC("llvm.cos.f64", "_ZGV4Nxv_cos", SCALABLE(4), "_ZGVr4Nxv")
TLI_DEFINE_VECFUNC("llvm.cos.f64", "_ZGV8Nxv_cos", SCALABLE(8), "_ZGVr8Nxv")

TLI_DEFINE_VECFUNC("tan", "_ZGV1Nxv_tan", SCALABLE(1), "_ZGVr1Nxv")
TLI_DEFINE_VECFUNC("tan", "_ZGV2Nxv_tan", SCALABLE(2), "_ZGVr2Nxv")
TLI_DEFINE_VECFUNC("tan", "_ZGV4Nxv_tan", SCALABLE(4), "_ZGVr4Nxv")
TLI_DEFINE_VECFUNC("tan", "_ZGV8Nxv_tan", SCALABLE(8), "_ZGVr8Nxv")

TLI_DEFINE_VECFUNC("llvm.tan.f64", "_ZGV1Nxv_tan", SCALABLE(1), "_ZGVr1Nxv")
TLI_DEFINE_VECFUNC("llvm.tan.f64", "_ZGV2Nxv_tan", SCALABLE(2), "_ZGVr2Nxv")
TLI_DEFINE_VECFUNC("llvm.tan.f64", "_ZGV4Nxv_tan", SCALABLE(4), "_ZGVr4Nxv")
TLI_DEFINE_VECFUNC("llvm.tan.f64", "_ZGV8Nxv_tan", SCALABLE(8), "_ZGVr8Nxv")

TLI_DEFINE_VECFUNC("pow", "_ZGV1Nxvv_pow", SCALABLE(1), "_ZGVr1Nxvv")
TLI_DEFINE_VECFUNC("pow", "_ZGV2Nxvv_pow", SCALABLE(2), "_ZGVr2Nxvv")
TLI_DEFINE_VECFUNC("pow", "_ZGV4Nxvv_pow", SCALABLE(4), "_ZGVr4Nxvv")
TLI_DEFINE_VECFUNC("pow", "_ZGV8Nxvv_pow", SCALABLE(8), "_ZGVr8Nxvv")

TLI_DEFINE_VECFUNC("llvm.pow.f64", "_ZGV1Nxvv_pow", SCALABLE(1), "_ZGVr1Nxvv")
TLI_DEFINE_VECFUNC("llvm.pow.f64", "_ZGV2Nxvv_pow", SCALABLE(2), "_ZGVr2Nxvv")
TLI_DEFINE_VECFUNC("llvm.pow.f64", "_ZGV4Nxvv_pow", SCALABLE(4), "_ZGVr4Nxvv")
TLI_DEFINE_VECFUNC("llvm.pow.f64", "_ZGV8Nxvv_pow", SCALABLE(8), "_ZGVr8Nxvv")

TLI_DEFINE_VECFUNC("exp", "_ZGV1Nxv_exp", SCALABLE(1), "_ZGVr1Nxv")
TLI_DEFINE_VECFUNC("exp", "_ZGV2Nxv_exp", SCALABLE(2), "_ZGVr2Nxv")
TLI_DEFINE_VECFUNC("exp", "_ZGV4Nxv_exp", SCALABLE(4), "_ZGVr4Nxv")
TLI_DEFINE_VECFUNC("exp", "_ZGV8Nxv_exp", SCALABLE(8), "_ZGVr8Nxv")

TLI_DEFINE_VECFUNC("expf", "_ZGV1Nxv_expf", SCALABLE(2), "_ZGVr1Nxv")
TLI_DEFINE_VECFUNC("expf", "_ZGV2Nxv_expf", SCALABLE(4), "_ZGVr2Nxv")
TLI_DEFINE_VECFUNC("expf", "_ZGV4Nxv_expf", SCALABLE(8), "_ZGVr4Nxv")
TLI_DEFINE_VECFUNC("expf", "_ZGV8Nxv_expf", SCALABLE(16), "_ZGVr8Nxv")

TLI_DEFINE_VECFUNC("llvm.exp.f64", "_ZGV1Nxv_exp", SCALABLE(1), "_ZGVr1Nxv")
TLI_DEFINE_VECFUNC("llvm.exp.f64", "_ZGV2Nxv_exp", SCALABLE(2), "_ZGVr2Nxv")
TLI_DEFINE_VECFUNC("llvm.exp.f64", "_ZGV4Nxv_exp", SCALABLE(4), "_ZGVr4Nxv")
TLI_DEFINE_VECFUNC("llvm.exp.f64", "_ZGV8Nxv_exp", SCALABLE(8), "_ZGVr8Nxv")

TLI_DEFINE_VECFUNC("llvm.exp.f32", "_ZGV1Nxv_expf", SCALABLE(2), "_ZGVr1Nxv")
TLI_DEFINE_VECFUNC("llvm.exp.f32", "_ZGV2Nxv_expf", SCALABLE(4), "_ZGVr2Nxv")
TLI_DEFINE_VECFUNC("llvm.exp.f32", "_ZGV4Nxv_expf", SCALABLE(8), "_ZGVr4Nxv")
TLI_DEFINE_VECFUNC("llvm.exp.f32", "_ZGV8Nxv_expf", SCALABLE(16), "_ZGVr8Nxv")

TLI_DEFINE_VECFUNC("log", "_ZGV1Nxv_log", SCALABLE(1), "_ZGVr1Nxv")
TLI_DEFINE_VECFUNC("log", "_ZGV2Nxv_log", SCALABLE(2), "_ZGVr2Nxv")
TLI_DEFINE_VECFUNC("log", "_ZGV4Nxv_log", SCALABLE(4), "_ZGVr4Nxv")
TLI_DEFINE_VECFUNC("log", "_ZGV8Nxv_log", SCALABLE(8), "_ZGVr8Nxv")

TLI_DEFINE_VECFUNC("llvm.log.f64", "_ZGV1Nxv_log", SCALABLE(1), "_ZGVr1Nxv")
TLI_DEFINE_VECFUNC("llvm.log.f64", "_ZGV2Nxv_log", SCALABLE(2), "_ZGVr2Nxv")
TLI_DEFINE_VECFUNC("llvm.log.f64", "_ZGV4Nxv_log", SCALABLE(4), "_ZGVr4Nxv")
TLI_DEFINE_VECFUNC("llvm.log.f64", "_ZGV8Nxv_log", SCALABLE(8), "_ZGVr8Nxv")

#elif defined(TLI_DEFINE_MASSV_VECFUNCS)
// IBM MASS library's vector Functions

Expand Down
4 changes: 4 additions & 0 deletions llvm/include/llvm/IR/VFABIDemangler.h
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Expand Up @@ -49,6 +49,10 @@ enum class VFISAKind {
AVX, // x86 AVX
AVX2, // x86 AVX2
AVX512, // x86 AVX512
RVVM1, // RISC-V Vector Extension LMUL=1
RVVM2, // RISC-V Vector Extension LMUL=2
RVVM4, // RISC-V Vector Extension LMUL=4
RVVM8, // RISC-V Vector Extension LMUL=8
Comment on lines +52 to +55
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@mag-mga mag-mga Dec 20, 2024

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Are you sure we need to enable all of them (now enabled only one for each RISC-V and AArch64)?

LLVM, // LLVM internal ISA for functions that are not
// attached to an existing ABI via name mangling.
Unknown // Unknown ISA
Expand Down
23 changes: 20 additions & 3 deletions llvm/lib/Analysis/TargetLibraryInfo.cpp
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Expand Up @@ -29,7 +29,7 @@ static cl::opt<TargetLibraryInfoImpl::VectorLibrary> ClVectorLibrary(
"Accelerate framework"),
clEnumValN(TargetLibraryInfoImpl::DarwinLibSystemM,
"Darwin_libsystem_m", "Darwin libsystem_m"),
clEnumValN(TargetLibraryInfoImpl::LIBMVEC_X86, "LIBMVEC-X86",
clEnumValN(TargetLibraryInfoImpl::LIBMVEC, "LIBMVEC",
"GLIBC Vector Math library"),
clEnumValN(TargetLibraryInfoImpl::MASSV, "MASSV",
"IBM MASS vector library"),
Expand Down Expand Up @@ -1291,6 +1291,12 @@ static const VecDesc VecFuncs_LIBMVEC_X86[] = {
#undef TLI_DEFINE_LIBMVEC_X86_VECFUNCS
};

static const VecDesc VecFuncs_LIBMVEC_RVV[] = {
#define TLI_DEFINE_LIBMVEC_RVV_VECFUNCS
#include "llvm/Analysis/VecFuncs.def"
#undef TLI_DEFINE_LIBMVEC_RVV_VECFUNCS
};

static const VecDesc VecFuncs_MASSV[] = {
#define TLI_DEFINE_MASSV_VECFUNCS
#include "llvm/Analysis/VecFuncs.def"
Expand Down Expand Up @@ -1360,8 +1366,19 @@ void TargetLibraryInfoImpl::addVectorizableFunctionsFromVecLib(
addVectorizableFunctions(VecFuncs_DarwinLibSystemM);
break;
}
case LIBMVEC_X86: {
addVectorizableFunctions(VecFuncs_LIBMVEC_X86);
case LIBMVEC: {
switch (TargetTriple.getArch()) {
default:
break;
case llvm::Triple::x86:
case llvm::Triple::x86_64:
addVectorizableFunctions(VecFuncs_LIBMVEC_X86);
break;
case llvm::Triple::riscv64:
case llvm::Triple::riscv32:
addVectorizableFunctions(VecFuncs_LIBMVEC_RVV);
break;
}
break;
}
case MASSV: {
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Frontend/Driver/CodeGenOptions.cpp
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Expand Up @@ -23,7 +23,7 @@ TargetLibraryInfoImpl *createTLII(llvm::Triple &TargetTriple,
TargetTriple);
break;
case VectorLibrary::LIBMVEC:
TLII->addVectorizableFunctionsFromVecLib(TargetLibraryInfoImpl::LIBMVEC_X86,
TLII->addVectorizableFunctionsFromVecLib(TargetLibraryInfoImpl::LIBMVEC,
TargetTriple);
break;
case VectorLibrary::MASSV:
Expand Down
69 changes: 57 additions & 12 deletions llvm/lib/IR/VFABIDemangler.cpp
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Expand Up @@ -38,11 +38,19 @@ static ParseRet tryParseISA(StringRef &MangledName, VFISAKind &ISA) {

if (MangledName.consume_front(VFABI::_LLVM_)) {
ISA = VFISAKind::LLVM;
} else if (MangledName.consume_front("r")) {
ISA = StringSwitch<VFISAKind>(MangledName.take_front(1))
.Case("1", VFISAKind::RVVM1)
.Case("2", VFISAKind::RVVM2)
.Case("4", VFISAKind::RVVM4)
.Case("8", VFISAKind::RVVM8)
.Default(VFISAKind::RVV);
if (ISA != VFISAKind::RVV)
MangledName = MangledName.drop_front(1);
} else {
ISA = StringSwitch<VFISAKind>(MangledName.take_front(1))
.Case("n", VFISAKind::AdvancedSIMD)
.Case("s", VFISAKind::SVE)
.Case("r", VFISAKind::RVV)
.Case("b", VFISAKind::SSE)
.Case("c", VFISAKind::AVX)
.Case("d", VFISAKind::AVX2)
Expand Down Expand Up @@ -79,8 +87,10 @@ static ParseRet tryParseMask(StringRef &MangledName, bool &IsMasked) {
static ParseRet tryParseVLEN(StringRef &ParseString, VFISAKind ISA,
std::pair<unsigned, bool> &ParsedVF) {
if (ParseString.consume_front("x")) {
// SVE is the only scalable ISA currently supported.
if (ISA != VFISAKind::SVE && ISA != VFISAKind::RVV) {
// SVE/RVV is the only two scalable ISAs currently supported.
if (ISA != VFISAKind::SVE && ISA != VFISAKind::RVV &&
ISA != VFISAKind::RVVM1 && ISA != VFISAKind::RVVM2 &&
ISA != VFISAKind::RVVM4 && ISA != VFISAKind::RVVM8) {
LLVM_DEBUG(dbgs() << "Vector function variant declared with scalable VF "
<< "but ISA supported for SVE and RVV only\n");
return ParseRet::Error;
Expand Down Expand Up @@ -302,17 +312,52 @@ static ParseRet tryParseAlign(StringRef &ParseString, Align &Alignment) {
// the number of elements of the given type which would fit in such a vector.
static std::optional<ElementCount> getElementCountForTy(const VFISAKind ISA,
const Type *Ty) {
assert((ISA == VFISAKind::SVE || ISA == VFISAKind::RVV) &&
// Only AArch64 SVE and RVV are supported at present.
assert((ISA == VFISAKind::SVE || ISA == VFISAKind::RVV ||
ISA == VFISAKind::RVVM1 || ISA == VFISAKind::RVVM2 ||
ISA == VFISAKind::RVVM4 || ISA == VFISAKind::RVVM8) &&
"Scalable VF decoding only implemented for SVE and RVV\n");

if (Ty->isIntegerTy(64) || Ty->isDoubleTy() || Ty->isPointerTy())
return ElementCount::getScalable(2);
if (Ty->isIntegerTy(32) || Ty->isFloatTy())
return ElementCount::getScalable(4);
if (Ty->isIntegerTy(16) || Ty->is16bitFPTy())
return ElementCount::getScalable(8);
if (Ty->isIntegerTy(8))
return ElementCount::getScalable(16);
if (ISA == VFISAKind::SVE || ISA == VFISAKind::RVV) {
if (Ty->isIntegerTy(64) || Ty->isDoubleTy() || Ty->isPointerTy())
return ElementCount::getScalable(2);
if (Ty->isIntegerTy(32) || Ty->isFloatTy())
return ElementCount::getScalable(4);
if (Ty->isIntegerTy(16) || Ty->is16bitFPTy())
return ElementCount::getScalable(8);
if (Ty->isIntegerTy(8))
return ElementCount::getScalable(16);
} else if (ISA == VFISAKind::RVVM1 || ISA == VFISAKind::RVVM2 ||
ISA == VFISAKind::RVVM4 || ISA == VFISAKind::RVVM8) {
// Because 'vscale = VLENB/8', so the ElementCount should be
// 'vscale x (LMUL * 64 / sizeof(Type))'.
unsigned Number = 1;
unsigned LMUL = 1;
unsigned ElemCount;

// TODO: need to distingush rv32 and rv64.
if (Ty->isPointerTy())
return std::nullopt;

if (Ty->isIntegerTy(64) || Ty->isDoubleTy())
Number = 1;
if (Ty->isIntegerTy(32) || Ty->isFloatTy())
Number = 2;
if (Ty->isIntegerTy(16) || Ty->is16bitFPTy())
Number = 4;
if (Ty->isIntegerTy(8))
Number = 8;

if (ISA == VFISAKind::RVVM2)
LMUL = 2;
else if (ISA == VFISAKind::RVVM4)
LMUL = 4;
else if (ISA == VFISAKind::RVVM8)
LMUL = 8;

ElemCount = LMUL * Number;
return ElementCount::getScalable(ElemCount);
}

return std::nullopt;
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Transforms/Utils/InjectTLIMappings.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -109,11 +109,11 @@ static void addMappingsFromTLI(const TargetLibraryInfo &TLI, CallInst &CI) {
TLI.getWidestVF(ScalarName, WidestFixedVF, WidestScalableVF);

for (bool Predicated : {false, true}) {
for (ElementCount VF = ElementCount::getFixed(2);
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@mag-mga mag-mga Dec 20, 2024

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Leave a comment about this change. It is unclear why this change is needed and whether it affects other vector libraries.

for (ElementCount VF = ElementCount::getFixed(1);
ElementCount::isKnownLE(VF, WidestFixedVF); VF *= 2)
AddVariantDecl(VF, Predicated);

for (ElementCount VF = ElementCount::getScalable(2);
for (ElementCount VF = ElementCount::getScalable(1);
ElementCount::isKnownLE(VF, WidestScalableVF); VF *= 2)
AddVariantDecl(VF, Predicated);
}
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18 changes: 9 additions & 9 deletions llvm/test/CodeGen/Generic/replace-intrinsics-with-veclib.ll
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes
; RUN: opt -vector-library=SVML -replace-with-veclib -S < %s | FileCheck %s --check-prefixes=COMMON,SVML
; RUN: opt -vector-library=AMDLIBM -replace-with-veclib -S < %s | FileCheck %s --check-prefixes=COMMON,AMDLIBM
; RUN: opt -vector-library=LIBMVEC-X86 -replace-with-veclib -S < %s | FileCheck %s --check-prefixes=COMMON,LIBMVEC-X86
; RUN: opt -vector-library=LIBMVEC -replace-with-veclib -S < %s | FileCheck %s --check-prefixes=COMMON,LIBMVEC
; RUN: opt -vector-library=MASSV -replace-with-veclib -S < %s | FileCheck %s --check-prefixes=COMMON,MASSV
; RUN: opt -vector-library=Accelerate -replace-with-veclib -S < %s | FileCheck %s --check-prefixes=COMMON,ACCELERATE

Expand All @@ -19,10 +19,10 @@ define <4 x double> @exp_v4(<4 x double> %in) {
; AMDLIBM-NEXT: [[TMP1:%.*]] = call <4 x double> @amd_vrd4_exp(<4 x double> [[IN]])
; AMDLIBM-NEXT: ret <4 x double> [[TMP1]]
;
; LIBMVEC-X86-LABEL: define {{[^@]+}}@exp_v4
; LIBMVEC-X86-SAME: (<4 x double> [[IN:%.*]]) {
; LIBMVEC-X86-NEXT: [[TMP1:%.*]] = call <4 x double> @_ZGVdN4v_exp(<4 x double> [[IN]])
; LIBMVEC-X86-NEXT: ret <4 x double> [[TMP1]]
; LIBMVEC-LABEL: define {{[^@]+}}@exp_v4
; LIBMVEC-SAME: (<4 x double> [[IN:%.*]]) {
; LIBMVEC-NEXT: [[TMP1:%.*]] = call <4 x double> @_ZGVdN4v_exp(<4 x double> [[IN]])
; LIBMVEC-NEXT: ret <4 x double> [[TMP1]]
;
; MASSV-LABEL: define {{[^@]+}}@exp_v4
; MASSV-SAME: (<4 x double> [[IN:%.*]]) {
Expand Down Expand Up @@ -51,10 +51,10 @@ define <4 x float> @exp_f32(<4 x float> %in) {
; AMDLIBM-NEXT: [[TMP1:%.*]] = call <4 x float> @amd_vrs4_expf(<4 x float> [[IN]])
; AMDLIBM-NEXT: ret <4 x float> [[TMP1]]
;
; LIBMVEC-X86-LABEL: define {{[^@]+}}@exp_f32
; LIBMVEC-X86-SAME: (<4 x float> [[IN:%.*]]) {
; LIBMVEC-X86-NEXT: [[TMP1:%.*]] = call <4 x float> @_ZGVbN4v_expf(<4 x float> [[IN]])
; LIBMVEC-X86-NEXT: ret <4 x float> [[TMP1]]
; LIBMVEC-LABEL: define {{[^@]+}}@exp_f32
; LIBMVEC-SAME: (<4 x float> [[IN:%.*]]) {
; LIBMVEC-NEXT: [[TMP1:%.*]] = call <4 x float> @_ZGVbN4v_expf(<4 x float> [[IN]])
; LIBMVEC-NEXT: ret <4 x float> [[TMP1]]
;
; MASSV-LABEL: define {{[^@]+}}@exp_f32
; MASSV-SAME: (<4 x float> [[IN:%.*]]) {
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