Skip to content

[GISel] Remove unnecessary MachineVerifier checks for G_ABDS/G_ABDU. #120014

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Dec 16, 2024
Merged

[GISel] Remove unnecessary MachineVerifier checks for G_ABDS/G_ABDU. #120014

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
25 changes: 0 additions & 25 deletions llvm/lib/CodeGen/MachineVerifier.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1586,31 +1586,6 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {

break;
}
case TargetOpcode::G_ABDS:
case TargetOpcode::G_ABDU: {
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
LLT SrcTy2 = MRI->getType(MI->getOperand(2).getReg());

if ((DstTy.isVector() != SrcTy.isVector()) ||
(DstTy.isVector() &&
DstTy.getElementCount() != SrcTy.getElementCount())) {
report("Generic vector abds/abdu must preserve number of lanes", MI);
break;
}

if (SrcTy != SrcTy2) {
report("Generic abds/abdu must have same input types", MI);
break;
}

if (DstTy != SrcTy) {
report("Generic abds/abdu must have same input and output types", MI);
break;
}

break;
}
case TargetOpcode::G_SCMP:
case TargetOpcode::G_UCMP: {
LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
Expand Down
13 changes: 10 additions & 3 deletions llvm/test/MachineVerifier/test_abd_su.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,25 +8,32 @@ body: |

%2:_(p0) = G_IMPLICIT_DEF
%3:_(p0) = G_IMPLICIT_DEF
; CHECK: Type mismatch in generic instruction
; CHECK: Type mismatch in generic instruction
%4:_(s1) = G_ABDS %2, %3

%12:_(s64) = G_IMPLICIT_DEF
%13:_(s64) = G_IMPLICIT_DEF
; CHECK: Type mismatch in generic instruction
; CHECK: Type mismatch in generic instruction
%14:_(p0) = G_ABDS %12, %13

%23:_(<2 x s32>) = G_IMPLICIT_DEF
%24:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: Generic vector abds/abdu must preserve number of lanes
; CHECK: Type mismatch in generic instruction
; CHECK: Type mismatch in generic instruction
%5:_(s1) = G_ABDU %23, %24

%15:_(s32) = G_CONSTANT i32 0
%16:_(s64) = G_CONSTANT i64 2
; CHECK: Generic abds/abdu must have same input types
; CHECK: Type mismatch in generic instruction
; CHECK: Type mismatch in generic instruction
%17:_(s1) = G_ABDU %15, %16

%18:_(s64) = G_CONSTANT i64 0
%19:_(s64) = G_CONSTANT i64 2
; CHECK: Generic abds/abdu must have same input and output types
; CHECK: Type mismatch in generic instruction
; CHECK: Type mismatch in generic instruction
%20:_(s1) = G_ABDU %18, %19

...
Expand Down
Loading