Skip to content

[RISCV][VLOPT] Add getOperandInfo for saturating signed multiply #120351

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Dec 30, 2024
Merged

[RISCV][VLOPT] Add getOperandInfo for saturating signed multiply #120351

Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
92a73e8
[RISCV][VLOPT] Add getOperandInfo for saturating signed multiply
michaelmaitland Dec 18, 2024
fc5c72c
fixup! add vsmul to isSupported
michaelmaitland Dec 18, 2024
34616c9
Revert "fixup! add vsmul to isSupported"
michaelmaitland Dec 30, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -378,6 +378,11 @@ static OperandInfo getOperandInfo(const MachineOperand &MO,
case RISCV::VASUBU_VX:
case RISCV::VASUB_VV:
case RISCV::VASUB_VX:
// Vector Single-Width Fractional Multiply with Rounding and Saturation
// EEW=SEW. EMUL=LMUL. The instruction produces 2*SEW product internally but
// saturates to fit into SEW bits.
case RISCV::VSMUL_VV:
case RISCV::VSMUL_VX:
// Vector Single-Width Scaling Shift Instructions
// EEW=SEW. EMUL=LMUL.
case RISCV::VSSRL_VI:
Expand Down
Loading