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[ARM] Use RegisterClassInfo::getRegPressureSetLimit #120377

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merged 2 commits into from
Dec 20, 2024
Merged

[ARM] Use RegisterClassInfo::getRegPressureSetLimit #120377

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[ARM] Use `RegisterClassInfo::getRegPressureSetLimit`
wangpc-pp Dec 18, 2024
c088417
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wangpc-pp Dec 19, 2024
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2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6979,7 +6979,7 @@ bool ARMPipelinerLoopInfo::tooMuchRegisterPressure(SwingSchedulerDAG &SSD,

auto &P = RPTracker.getPressure().MaxSetPressure;
for (unsigned I = 0, E = P.size(); I < E; ++I)
if (P[I] > TRI->getRegPressureSetLimit(*MF, I)) {
if (P[I] > RegClassInfo.getRegPressureSetLimit(I)) {
return true;
}
return false;
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75 changes: 32 additions & 43 deletions llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -17,69 +17,58 @@ define void @arm_cmplx_dot_prod_q15(ptr noundef %pSrcA, ptr noundef %pSrcB, i32
; CHECK-NEXT: mov.w r5, #0
; CHECK-NEXT: csel r7, r6, r5, hs
; CHECK-NEXT: add.w lr, r7, #1
; CHECK-NEXT: mov r4, r5
; CHECK-NEXT: vldrh.u16 q0, [r0], #32
; CHECK-NEXT: mov r6, r5
; CHECK-NEXT: vldrh.u16 q1, [r0], #32
; CHECK-NEXT: movs r7, #0
; CHECK-NEXT: mov r8, r5
; CHECK-NEXT: vldrh.u16 q1, [r1], #32
; CHECK-NEXT: vmlsldava.s16 r4, r7, q0, q1
; CHECK-NEXT: vldrh.u16 q2, [r0, #-16]
; CHECK-NEXT: vmlaldavax.s16 r8, r5, q0, q1
; CHECK-NEXT: vldrh.u16 q3, [r1, #-16]
; CHECK-NEXT: vmlsldava.s16 r4, r7, q2, q3
; CHECK-NEXT: vldrh.u16 q0, [r1], #32
; CHECK-NEXT: sub.w lr, lr, #1
; CHECK-NEXT: cmp.w lr, #0
; CHECK-NEXT: vldrh.u16 q1, [r0], #32
; CHECK-NEXT: beq .LBB0_3
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: .LBB0_2: @ %while.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vmlaldavax.s16 r8, r5, q2, q3
; CHECK-NEXT: vldrh.u16 q3, [r1, #-16]
; CHECK-NEXT: vmlsldava.s16 r4, r7, q1, q0
; CHECK-NEXT: vmlsldava.s16 r8, r7, q1, q0
; CHECK-NEXT: vldrh.u16 q2, [r0, #-16]
; CHECK-NEXT: vmlaldavax.s16 r8, r5, q1, q0
; CHECK-NEXT: vldrh.u16 q1, [r0], #32
; CHECK-NEXT: vmlsldava.s16 r4, r7, q2, q3
; CHECK-NEXT: vmlaldavax.s16 r6, r5, q1, q0
; CHECK-NEXT: vldrh.u16 q1, [r1, #-16]
; CHECK-NEXT: vmlsldava.s16 r8, r7, q2, q1
; CHECK-NEXT: vldrh.u16 q0, [r1], #32
; CHECK-NEXT: vmlaldavax.s16 r6, r5, q2, q1
; CHECK-NEXT: vldrh.u16 q1, [r0], #32
; CHECK-NEXT: le lr, .LBB0_2
; CHECK-NEXT: .LBB0_3:
; CHECK-NEXT: vmlaldavax.s16 r8, r5, q2, q3
; CHECK-NEXT: movs r6, #14
; CHECK-NEXT: and.w r2, r6, r2, lsl #1
; CHECK-NEXT: vmlaldavax.s16 r8, r5, q1, q0
; CHECK-NEXT: @ %bb.3: @ %do.body
; CHECK-NEXT: movs r4, #14
; CHECK-NEXT: and.w r2, r4, r2, lsl #1
; CHECK-NEXT: vmlaldavax.s16 r6, r5, q1, q0
; CHECK-NEXT: vldrh.u16 q2, [r0, #-16]
; CHECK-NEXT: vmlsldava.s16 r4, r7, q1, q0
; CHECK-NEXT: vmlsldava.s16 r8, r7, q1, q0
; CHECK-NEXT: vldrh.u16 q0, [r1, #-16]
; CHECK-NEXT: vmlaldavax.s16 r8, r5, q2, q0
; CHECK-NEXT: vmlaldavax.s16 r6, r5, q2, q0
; CHECK-NEXT: vctp.16 r2
; CHECK-NEXT: vmlsldava.s16 r4, r7, q2, q0
; CHECK-NEXT: vmlsldava.s16 r8, r7, q2, q0
; CHECK-NEXT: vpst
; CHECK-NEXT: vldrht.u16 q1, [r0]
; CHECK-NEXT: cmp r2, #9
; CHECK-NEXT: vpsttt
; CHECK-NEXT: vldrht.u16 q0, [r1]
; CHECK-NEXT: vmlsldavat.s16 r4, r7, q1, q0
; CHECK-NEXT: vmlaldavaxt.s16 r8, r5, q1, q0
; CHECK-NEXT: vmlsldavat.s16 r8, r7, q1, q0
; CHECK-NEXT: vmlaldavaxt.s16 r6, r5, q1, q0
; CHECK-NEXT: blo .LBB0_10
; CHECK-NEXT: @ %bb.4: @ %do.body.1
; CHECK-NEXT: subs r2, #8
; CHECK-NEXT: vctp.16 r2
; CHECK-NEXT: vpstttt
; CHECK-NEXT: vldrht.u16 q0, [r0, #16]
; CHECK-NEXT: vldrht.u16 q1, [r1, #16]
; CHECK-NEXT: vmlsldavat.s16 r4, r7, q0, q1
; CHECK-NEXT: vmlaldavaxt.s16 r8, r5, q0, q1
; CHECK-NEXT: vmlsldavat.s16 r8, r7, q0, q1
; CHECK-NEXT: vmlaldavaxt.s16 r6, r5, q0, q1
; CHECK-NEXT: b .LBB0_10
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: .LBB0_5: @ %if.else
; CHECK-NEXT: mov.w r4, #0
; CHECK-NEXT: mov.w r8, #0
; CHECK-NEXT: cbz r2, .LBB0_9
; CHECK-NEXT: @ %bb.6: @ %while.body14.preheader
; CHECK-NEXT: lsls r6, r2, #1
; CHECK-NEXT: mov r5, r4
; CHECK-NEXT: mov r7, r4
; CHECK-NEXT: mov r5, r8
; CHECK-NEXT: mov r7, r8
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: dlstp.16 lr, r6
; CHECK-NEXT: .p2align 2
Expand All @@ -88,22 +77,22 @@ define void @arm_cmplx_dot_prod_q15(ptr noundef %pSrcA, ptr noundef %pSrcB, i32
; CHECK-NEXT: vldrh.u16 q0, [r0], #16
; CHECK-NEXT: vldrh.u16 q1, [r1], #16
; CHECK-NEXT: vmlsldava.s16 r2, r7, q0, q1
; CHECK-NEXT: vmlaldavax.s16 r4, r5, q0, q1
; CHECK-NEXT: vmlaldavax.s16 r8, r5, q0, q1
; CHECK-NEXT: letp lr, .LBB0_7
; CHECK-NEXT: @ %bb.8: @ %if.end.loopexit177
; CHECK-NEXT: mov r8, r4
; CHECK-NEXT: mov r4, r2
; CHECK-NEXT: mov r6, r8
; CHECK-NEXT: mov r8, r2
; CHECK-NEXT: b .LBB0_10
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: .LBB0_9:
; CHECK-NEXT: mov r7, r4
; CHECK-NEXT: mov.w r8, #0
; CHECK-NEXT: mov r5, r4
; CHECK-NEXT: mov r7, r8
; CHECK-NEXT: movs r6, #0
; CHECK-NEXT: mov r5, r8
; CHECK-NEXT: .LBB0_10: @ %if.end
; CHECK-NEXT: asrl r4, r7, #6
; CHECK-NEXT: asrl r8, r5, #6
; CHECK-NEXT: str r4, [r3]
; CHECK-NEXT: str.w r8, [r12]
; CHECK-NEXT: asrl r8, r7, #6
; CHECK-NEXT: asrl r6, r5, #6
; CHECK-NEXT: str.w r8, [r3]
; CHECK-NEXT: str.w r6, [r12]
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
entry:
%cmp = icmp ugt i32 %numSamples, 15
Expand Down
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