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[AMDGPU][True16][MC] true16 for v_frexp_mant_f16 #120653

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Merged
merged 1 commit into from
Jan 3, 2025
+1,298 −465
Merged

[AMDGPU][True16][MC] true16 for v_frexp_mant_f16 #120653

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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/VOP1Instructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1036,7 +1036,7 @@ defm V_LOG_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x057, "v_log_f16"
defm V_LOG_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x057, "v_log_f16">;
defm V_EXP_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x058, "v_exp_f16">;
defm V_EXP_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x058, "v_exp_f16">;
defm V_FREXP_MANT_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x059, "v_frexp_mant_f16">;
defm V_FREXP_MANT_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x059, "v_frexp_mant_f16">;
defm V_FREXP_EXP_I16_F16 : VOP1_Real_FULL_t16_and_fake16_gfx11_gfx12<0x05a, "v_frexp_exp_i16_f16">;
defm V_FLOOR_F16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05b, "v_floor_f16">;
defm V_FLOOR_F16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x05b, "v_floor_f16">;
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262 changes: 262 additions & 0 deletions llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
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75 changes: 45 additions & 30 deletions llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
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Expand Up @@ -2351,50 +2351,65 @@ v_frexp_exp_i32_f64 v5, src_scc
v_frexp_exp_i32_f64 v255, 0xaf123456
// GFX11: v_frexp_exp_i32_f64_e32 v255, 0xaf123456 ; encoding: [0xff,0x78,0xfe,0x7f,0x56,0x34,0x12,0xaf]

v_frexp_mant_f16 v5, v1
// GFX11: v_frexp_mant_f16_e32 v5, v1 ; encoding: [0x01,0xb3,0x0a,0x7e]
v_frexp_mant_f16 v5.l, v1.l
// GFX11: v_frexp_mant_f16_e32 v5.l, v1.l ; encoding: [0x01,0xb3,0x0a,0x7e]

v_frexp_mant_f16 v5, v127
// GFX11: v_frexp_mant_f16_e32 v5, v127 ; encoding: [0x7f,0xb3,0x0a,0x7e]
v_frexp_mant_f16 v5.l, v127.l
// GFX11: v_frexp_mant_f16_e32 v5.l, v127.l ; encoding: [0x7f,0xb3,0x0a,0x7e]

v_frexp_mant_f16 v5, s1
// GFX11: v_frexp_mant_f16_e32 v5, s1 ; encoding: [0x01,0xb2,0x0a,0x7e]
v_frexp_mant_f16 v5.l, s1
// GFX11: v_frexp_mant_f16_e32 v5.l, s1 ; encoding: [0x01,0xb2,0x0a,0x7e]

v_frexp_mant_f16 v5, s105
// GFX11: v_frexp_mant_f16_e32 v5, s105 ; encoding: [0x69,0xb2,0x0a,0x7e]
v_frexp_mant_f16 v5.l, s105
// GFX11: v_frexp_mant_f16_e32 v5.l, s105 ; encoding: [0x69,0xb2,0x0a,0x7e]

v_frexp_mant_f16 v5, vcc_lo
// GFX11: v_frexp_mant_f16_e32 v5, vcc_lo ; encoding: [0x6a,0xb2,0x0a,0x7e]
v_frexp_mant_f16 v5.l, vcc_lo
// GFX11: v_frexp_mant_f16_e32 v5.l, vcc_lo ; encoding: [0x6a,0xb2,0x0a,0x7e]

v_frexp_mant_f16 v5, vcc_hi
// GFX11: v_frexp_mant_f16_e32 v5, vcc_hi ; encoding: [0x6b,0xb2,0x0a,0x7e]
v_frexp_mant_f16 v5.l, vcc_hi
// GFX11: v_frexp_mant_f16_e32 v5.l, vcc_hi ; encoding: [0x6b,0xb2,0x0a,0x7e]

v_frexp_mant_f16 v5, ttmp15
// GFX11: v_frexp_mant_f16_e32 v5, ttmp15 ; encoding: [0x7b,0xb2,0x0a,0x7e]
v_frexp_mant_f16 v5.l, ttmp15
// GFX11: v_frexp_mant_f16_e32 v5.l, ttmp15 ; encoding: [0x7b,0xb2,0x0a,0x7e]

v_frexp_mant_f16 v5, m0
// GFX11: v_frexp_mant_f16_e32 v5, m0 ; encoding: [0x7d,0xb2,0x0a,0x7e]
v_frexp_mant_f16 v5.l, m0
// GFX11: v_frexp_mant_f16_e32 v5.l, m0 ; encoding: [0x7d,0xb2,0x0a,0x7e]

v_frexp_mant_f16 v5, exec_lo
// GFX11: v_frexp_mant_f16_e32 v5, exec_lo ; encoding: [0x7e,0xb2,0x0a,0x7e]
v_frexp_mant_f16 v5.l, exec_lo
// GFX11: v_frexp_mant_f16_e32 v5.l, exec_lo ; encoding: [0x7e,0xb2,0x0a,0x7e]

v_frexp_mant_f16 v5, exec_hi
// GFX11: v_frexp_mant_f16_e32 v5, exec_hi ; encoding: [0x7f,0xb2,0x0a,0x7e]
v_frexp_mant_f16 v5.l, exec_hi
// GFX11: v_frexp_mant_f16_e32 v5.l, exec_hi ; encoding: [0x7f,0xb2,0x0a,0x7e]

v_frexp_mant_f16 v5, null
// GFX11: v_frexp_mant_f16_e32 v5, null ; encoding: [0x7c,0xb2,0x0a,0x7e]
v_frexp_mant_f16 v5.l, null
// GFX11: v_frexp_mant_f16_e32 v5.l, null ; encoding: [0x7c,0xb2,0x0a,0x7e]

v_frexp_mant_f16 v5, -1
// GFX11: v_frexp_mant_f16_e32 v5, -1 ; encoding: [0xc1,0xb2,0x0a,0x7e]
v_frexp_mant_f16 v5.l, -1
// GFX11: v_frexp_mant_f16_e32 v5.l, -1 ; encoding: [0xc1,0xb2,0x0a,0x7e]

v_frexp_mant_f16 v5, 0.5
// GFX11: v_frexp_mant_f16_e32 v5, 0.5 ; encoding: [0xf0,0xb2,0x0a,0x7e]
v_frexp_mant_f16 v5.l, 0.5
// GFX11: v_frexp_mant_f16_e32 v5.l, 0.5 ; encoding: [0xf0,0xb2,0x0a,0x7e]

v_frexp_mant_f16 v5, src_scc
// GFX11: v_frexp_mant_f16_e32 v5, src_scc ; encoding: [0xfd,0xb2,0x0a,0x7e]
v_frexp_mant_f16 v5.l, src_scc
// GFX11: v_frexp_mant_f16_e32 v5.l, src_scc ; encoding: [0xfd,0xb2,0x0a,0x7e]

v_frexp_mant_f16 v127, 0xfe0b
// GFX11: v_frexp_mant_f16_e32 v127, 0xfe0b ; encoding: [0xff,0xb2,0xfe,0x7e,0x0b,0xfe,0x00,0x00]
v_frexp_mant_f16 v127.l, 0xfe0b
// GFX11: v_frexp_mant_f16_e32 v127.l, 0xfe0b ; encoding: [0xff,0xb2,0xfe,0x7e,0x0b,0xfe,0x00,0x00]

v_frexp_mant_f16 v5.l, v1.h
// GFX11: v_frexp_mant_f16_e32 v5.l, v1.h ; encoding: [0x81,0xb3,0x0a,0x7e]

v_frexp_mant_f16 v5.l, v127.h
// GFX11: v_frexp_mant_f16_e32 v5.l, v127.h ; encoding: [0xff,0xb3,0x0a,0x7e]

v_frexp_mant_f16 v127.l, 0.5
// GFX11: v_frexp_mant_f16_e32 v127.l, 0.5 ; encoding: [0xf0,0xb2,0xfe,0x7e]

v_frexp_mant_f16 v5.h, src_scc
// GFX11: v_frexp_mant_f16_e32 v5.h, src_scc ; encoding: [0xfd,0xb2,0x0a,0x7f]

v_frexp_mant_f16 v127.h, 0xfe0b
// GFX11: v_frexp_mant_f16_e32 v127.h, 0xfe0b ; encoding: [0xff,0xb2,0xfe,0x7f,0x0b,0xfe,0x00,0x00]

v_frexp_mant_f32 v5, v1
// GFX11: v_frexp_mant_f32_e32 v5, v1 ; encoding: [0x01,0x81,0x0a,0x7e]
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65 changes: 37 additions & 28 deletions llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
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Expand Up @@ -1766,47 +1766,56 @@ v_frexp_exp_i32_f32 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 f
v_frexp_exp_i32_f32 v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: v_frexp_exp_i32_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x7e,0xfe,0x7f,0xff,0x6f,0x35,0x30]

v_frexp_mant_f16 v5, v1 quad_perm:[3,2,1,0]
// GFX11: v_frexp_mant_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x1b,0x00,0xff]
v_frexp_mant_f16 v5.l, v1.l quad_perm:[3,2,1,0]
// GFX11: v_frexp_mant_f16_dpp v5.l, v1.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x1b,0x00,0xff]

v_frexp_mant_f16 v5, v1 quad_perm:[0,1,2,3]
// GFX11: v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0xff]
v_frexp_mant_f16 v5.l, v1.l quad_perm:[0,1,2,3]
// GFX11: v_frexp_mant_f16_dpp v5.l, v1.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0xff]

v_frexp_mant_f16 v5, v1 row_mirror
// GFX11: v_frexp_mant_f16_dpp v5, v1 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x40,0x01,0xff]
v_frexp_mant_f16 v5.l, v1.l row_mirror
// GFX11: v_frexp_mant_f16_dpp v5.l, v1.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x40,0x01,0xff]

v_frexp_mant_f16 v5, v1 row_half_mirror
// GFX11: v_frexp_mant_f16_dpp v5, v1 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x41,0x01,0xff]
v_frexp_mant_f16 v5.l, v1.l row_half_mirror
// GFX11: v_frexp_mant_f16_dpp v5.l, v1.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x41,0x01,0xff]

v_frexp_mant_f16 v5, v1 row_shl:1
// GFX11: v_frexp_mant_f16_dpp v5, v1 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x01,0x01,0xff]
v_frexp_mant_f16 v5.l, v1.l row_shl:1
// GFX11: v_frexp_mant_f16_dpp v5.l, v1.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x01,0x01,0xff]

v_frexp_mant_f16 v5, v1 row_shl:15
// GFX11: v_frexp_mant_f16_dpp v5, v1 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x0f,0x01,0xff]
v_frexp_mant_f16 v5.l, v1.l row_shl:15
// GFX11: v_frexp_mant_f16_dpp v5.l, v1.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x0f,0x01,0xff]

v_frexp_mant_f16 v5, v1 row_shr:1
// GFX11: v_frexp_mant_f16_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x11,0x01,0xff]
v_frexp_mant_f16 v5.l, v1.l row_shr:1
// GFX11: v_frexp_mant_f16_dpp v5.l, v1.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x11,0x01,0xff]

v_frexp_mant_f16 v5, v1 row_shr:15
// GFX11: v_frexp_mant_f16_dpp v5, v1 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x1f,0x01,0xff]
v_frexp_mant_f16 v5.l, v1.l row_shr:15
// GFX11: v_frexp_mant_f16_dpp v5.l, v1.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x1f,0x01,0xff]

v_frexp_mant_f16 v5, v1 row_ror:1
// GFX11: v_frexp_mant_f16_dpp v5, v1 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x21,0x01,0xff]
v_frexp_mant_f16 v5.l, v1.l row_ror:1
// GFX11: v_frexp_mant_f16_dpp v5.l, v1.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x21,0x01,0xff]

v_frexp_mant_f16 v5, v1 row_ror:15
// GFX11: v_frexp_mant_f16_dpp v5, v1 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x2f,0x01,0xff]
v_frexp_mant_f16 v5.l, v1.l row_ror:15
// GFX11: v_frexp_mant_f16_dpp v5.l, v1.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x2f,0x01,0xff]

v_frexp_mant_f16 v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
// GFX11: v_frexp_mant_f16_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x50,0x01,0xff]
v_frexp_mant_f16 v5.l, v1.l row_share:0 row_mask:0xf bank_mask:0xf
// GFX11: v_frexp_mant_f16_dpp v5.l, v1.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x50,0x01,0xff]

v_frexp_mant_f16 v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1
// GFX11: v_frexp_mant_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x5f,0x01,0x01]
v_frexp_mant_f16 v5.l, v1.l row_share:15 row_mask:0x0 bank_mask:0x1
// GFX11: v_frexp_mant_f16_dpp v5.l, v1.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x5f,0x01,0x01]

v_frexp_mant_f16 v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
// GFX11: v_frexp_mant_f16_dpp v5, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x60,0x09,0x13]
v_frexp_mant_f16 v5.l, v1.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
// GFX11: v_frexp_mant_f16_dpp v5.l, v1.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x60,0x09,0x13]

v_frexp_mant_f16 v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: v_frexp_mant_f16_dpp v127, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xb2,0xfe,0x7e,0x7f,0x6f,0x35,0x30]
v_frexp_mant_f16 v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
// GFX11: v_frexp_mant_f16_dpp v127.l, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xb2,0xfe,0x7e,0x7f,0x6f,0x35,0x30]

v_frexp_mant_f16 v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
// GFX11: v_frexp_mant_f16_dpp v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xb2,0xfe,0x7e,0x7f,0x5f,0x01,0x01]

v_frexp_mant_f16 v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
// GFX11: v_frexp_mant_f16_dpp v5.h, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0xb2,0x0a,0x7f,0x81,0x60,0x09,0x13]

v_frexp_mant_f16 v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
// GFX11: v_frexp_mant_f16_dpp v127.h, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xb2,0xfe,0x7f,0xff,0x6f,0x35,0x30]

v_frexp_mant_f32 v5, v1 quad_perm:[3,2,1,0]
// GFX11: v_frexp_mant_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x00,0xff]
Expand Down
21 changes: 15 additions & 6 deletions llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
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Original file line number Diff line number Diff line change
Expand Up @@ -416,14 +416,23 @@ v_frexp_exp_i32_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
v_frexp_exp_i32_f32 v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: v_frexp_exp_i32_f32_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0x7e,0xfe,0x7f,0xff,0x00,0x00,0x00]

v_frexp_mant_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_frexp_mant_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0x0a,0x7e,0x01,0x77,0x39,0x05]
v_frexp_mant_f16 v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_frexp_mant_f16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0x0a,0x7e,0x01,0x77,0x39,0x05]

v_frexp_mant_f16 v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
// GFX11: v_frexp_mant_f16_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xb2,0x0a,0x7e,0x01,0x77,0x39,0x05]
v_frexp_mant_f16 v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1
// GFX11: v_frexp_mant_f16_dpp v5.l, v1.l dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xb2,0x0a,0x7e,0x01,0x77,0x39,0x05]

v_frexp_mant_f16 v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: v_frexp_mant_f16_dpp v127, v127 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xb2,0xfe,0x7e,0x7f,0x00,0x00,0x00]
v_frexp_mant_f16 v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0]
// GFX11: v_frexp_mant_f16_dpp v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xb2,0xfe,0x7e,0x7f,0x00,0x00,0x00]

v_frexp_mant_f16 v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_frexp_mant_f16_dpp v127.l, v127.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0xb2,0xfe,0x7e,0x7f,0x77,0x39,0x05]

v_frexp_mant_f16 v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] fi:1
// GFX11: v_frexp_mant_f16_dpp v5.h, v1.h dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0xb2,0x0a,0x7f,0x81,0x77,0x39,0x05]

v_frexp_mant_f16 v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:0
// GFX11: v_frexp_mant_f16_dpp v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0xb2,0xfe,0x7f,0xff,0x00,0x00,0x00]

v_frexp_mant_f32 v5, v1 dpp8:[7,6,5,4,3,2,1,0]
// GFX11: v_frexp_mant_f32_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x80,0x0a,0x7e,0x01,0x77,0x39,0x05]
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42 changes: 42 additions & 0 deletions llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
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Original file line number Diff line number Diff line change
Expand Up @@ -521,6 +521,12 @@ v_frexp_exp_i16_f16_e32 v5.l, v199.l quad_perm:[3,2,1,0]
v_frexp_mant_f16_e32 v128, 0xfe0b
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode

v_frexp_mant_f16_e32 v128.h, 0xfe0b
// GFX11: :[[@LINE-1]]:22: error: invalid operand for instruction

v_frexp_mant_f16_e32 v128.l, 0xfe0b
// GFX11: :[[@LINE-1]]:22: error: invalid operand for instruction

v_frexp_mant_f16_e32 v255, v1
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode

Expand All @@ -530,6 +536,24 @@ v_frexp_mant_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
v_frexp_mant_f16_e32 v255, v1 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction

v_frexp_mant_f16_e32 v255.h, v1.h
// GFX11: :[[@LINE-1]]:22: error: invalid operand for instruction

v_frexp_mant_f16_e32 v255.h, v1.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:22: error: invalid operand for instruction

v_frexp_mant_f16_e32 v255.h, v1.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:22: error: invalid operand for instruction

v_frexp_mant_f16_e32 v255.l, v1.l
// GFX11: :[[@LINE-1]]:22: error: invalid operand for instruction

v_frexp_mant_f16_e32 v255.l, v1.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:22: error: invalid operand for instruction

v_frexp_mant_f16_e32 v255.l, v1.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:22: error: invalid operand for instruction

v_frexp_mant_f16_e32 v5, v199
// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode

Expand All @@ -539,6 +563,24 @@ v_frexp_mant_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
v_frexp_mant_f16_e32 v5, v199 quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:31: error: invalid operand for instruction

v_frexp_mant_f16_e32 v5.h, v199.h
// GFX11: :[[@LINE-1]]:28: error: invalid operand for instruction

v_frexp_mant_f16_e32 v5.h, v199.h dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:28: error: invalid operand for instruction

v_frexp_mant_f16_e32 v5.h, v199.h quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:28: error: invalid operand for instruction

v_frexp_mant_f16_e32 v5.l, v199.l
// GFX11: :[[@LINE-1]]:28: error: invalid operand for instruction

v_frexp_mant_f16_e32 v5.l, v199.l dpp8:[7,6,5,4,3,2,1,0]
// GFX11: :[[@LINE-1]]:28: error: invalid operand for instruction

v_frexp_mant_f16_e32 v5.l, v199.l quad_perm:[3,2,1,0]
// GFX11: :[[@LINE-1]]:28: error: invalid operand for instruction

v_log_f16_e32 v128.h, 0xfe0b
// GFX11: :[[@LINE-1]]:15: error: invalid operand for instruction

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