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4 changes: 4 additions & 0 deletions llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3793,6 +3793,8 @@ EVT HexagonTargetLowering::getOptimalMemOpType(
bool HexagonTargetLowering::allowsMemoryAccess(
LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const {
if (!VT.isSimple())
return false;
MVT SVT = VT.getSimpleVT();
if (Subtarget.isHVXVectorType(SVT, true))
return allowsHvxMemoryAccess(SVT, Flags, Fast);
Expand All @@ -3803,6 +3805,8 @@ bool HexagonTargetLowering::allowsMemoryAccess(
bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(
EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
unsigned *Fast) const {
if (!VT.isSimple())
return false;
MVT SVT = VT.getSimpleVT();
if (Subtarget.isHVXVectorType(SVT, true))
return allowsHvxMisalignedMemoryAccesses(SVT, Flags, Fast);
Expand Down
22 changes: 22 additions & 0 deletions llvm/test/CodeGen/Hexagon/simple-types-mem.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@
; RUN: llc -march=hexagon < %s
; REQUIRES: asserts

; Only simple types memory accesses are handled.

target triple = "hexagon"

%struct.hoge = type { i320 }

define dso_local void @widget() {
bb:
%tmp = alloca %struct.hoge, align 1
%tmp1 = bitcast %struct.hoge* %tmp to i320*
%tmp2 = load i320, i320* %tmp1, align 1
%tmp3 = and i320 %tmp2, -18446744073709551616
%tmp4 = or i320 %tmp3, 0
store i320 %tmp4, i320* %tmp1, align 1
call void @llvm.trap()
unreachable
}

declare void @llvm.trap()
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