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[Hexagon] Add missing pattern for v8i1 type #120703

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Merged
merged 3 commits into from
Jan 10, 2025
Merged

[Hexagon] Add missing pattern for v8i1 type #120703

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84727b6
[Hexagon] Add missing pattern for v8i1 type
quic-santdas Sep 22, 2024
81be1c4
Merge branch 'main' into Patternv8i1
quic-santdas Jan 8, 2025
a677bf7
Merge branch 'main' into Patternv8i1
quic-santdas Jan 9, 2025
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3 changes: 3 additions & 0 deletions llvm/lib/Target/Hexagon/HexagonPatterns.td
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Original file line number Diff line number Diff line change
Expand Up @@ -108,6 +108,9 @@ def ptrue: PatFrag<(ops), (HexagonPTRUE)>;
def pfalse: PatFrag<(ops), (HexagonPFALSE)>;
def pnot: PatFrag<(ops node:$Pu), (xor node:$Pu, ptrue)>;

def: Pat<(v8i1 (HexagonPFALSE)), (C2_tfrrp (A2_tfrsi (i32 0)))>;
def: Pat<(v8i1 (HexagonPTRUE)), (C2_tfrrp (A2_tfrsi (i32 -1)))>;

def valign: PatFrag<(ops node:$Vt, node:$Vs, node:$Ru),
(HexagonVALIGN node:$Vt, node:$Vs, node:$Ru)>;
def valignaddr: PatFrag<(ops node:$Addr), (HexagonVALIGNADDR node:$Addr)>;
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15 changes: 15 additions & 0 deletions llvm/test/CodeGen/Hexagon/isel/isel-tfrrp.ll
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@@ -0,0 +1,15 @@
; Check if a C2_tfrrp instruction with constant i32 0 input is generated
; The constant 0 is generated by a transfer immediate instruction.

; RUN: llc -march=hexagon -debug-only=isel 2>&1 < %s - | FileCheck %s

; CHECK: [[R0:%[0-9]+]]:intregs = A2_tfrsi 0
; CHECK-NEXT: predregs = C2_tfrrp killed [[R0]]:intregs

define void @test_false(i1 %0) {
%2 = insertelement <1024 x i1> zeroinitializer, i1 %0, i64 0
tail call void @llvm.masked.store.v1024f32.p0(<1024 x float> zeroinitializer, ptr null, i32 1, <1024 x i1> %2)
ret void
}

declare void @llvm.masked.store.v1024f32.p0(<1024 x float>, ptr nocapture, i32 immarg, <1024 x i1>)
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