[AMDGPU] Support dynamically sized allocas

[easyonaadit]

Stack space is computed by applying wave-wide reduction on alloca's size argument.

[github-actions]

⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️

You can test this locally with the following command:

git-clang-format --diff c7606710f93cf0ab655a5bcbbf873954051ba109 26343cc11f1773da49e23555c74a44ef5cbf3a4a --extensions cpp -- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp

View the diff from clang-format here.

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index fb0e111d2c..414f67ec1c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -1191,11 +1191,12 @@ bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc(
   const RegisterBank *SizeBank = getRegBank(AllocSize, MRI, *TRI);
 
   // TODO: Need to emit a wave reduction to get the maximum size.
-  if (SizeBank != &AMDGPU::SGPRRegBank){
-    auto WaveReduction = B.buildIntrinsic(Intrinsic::amdgcn_wave_reduce_umax,
-                             {LLT::scalar(MRI.getType(AllocSize).getSizeInBits())})
-                .addUse(AllocSize)
-                .addImm(0);
+  if (SizeBank != &AMDGPU::SGPRRegBank) {
+    auto WaveReduction =
+        B.buildIntrinsic(Intrinsic::amdgcn_wave_reduce_umax,
+                         {LLT::scalar(MRI.getType(AllocSize).getSizeInBits())})
+            .addUse(AllocSize)
+            .addImm(0);
     AllocSize = WaveReduction.getReg(0);
   }
 
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index fb316343c6..3c0a7e0fca 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4059,26 +4059,26 @@ SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
   }
 
   SDValue NewSP;
-  if (isa<ConstantSDNode>(Op.getOperand(1))){
+  if (isa<ConstantSDNode>(Op.getOperand(1))) {
     SDValue ScaledSize = DAG.getNode(
         ISD::SHL, dl, VT, Size,
         DAG.getConstant(Subtarget->getWavefrontSizeLog2(), dl, MVT::i32));
     NewSP = DAG.getNode(ISD::ADD, dl, VT, BaseAddr, ScaledSize); // Value
-  }
-  else{
+  } else {
     // performing a wave reduction to get the maximum size
     SDValue WaveReduction =
         DAG.getTargetConstant(Intrinsic::amdgcn_wave_reduce_umax, dl, MVT::i32);
-    Size = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
-                          WaveReduction, Size, DAG.getConstant(0, dl, MVT::i32));
+    Size = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, WaveReduction,
+                       Size, DAG.getConstant(0, dl, MVT::i32));
     SDValue ScaledSize = DAG.getNode(
         ISD::SHL, dl, VT, Size,
         DAG.getConstant(Subtarget->getWavefrontSizeLog2(), dl, MVT::i32));
-    NewSP = DAG.getNode(ISD::ADD, dl, VT, BaseAddr, ScaledSize); // Value in vgpr.
+    NewSP =
+        DAG.getNode(ISD::ADD, dl, VT, BaseAddr, ScaledSize); // Value in vgpr.
     SDValue ReadFirstLaneID =
         DAG.getTargetConstant(Intrinsic::amdgcn_readfirstlane, dl, MVT::i32);
-    NewSP = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
-                          ReadFirstLaneID, NewSP);
+    NewSP = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, ReadFirstLaneID,
+                        NewSP);
   }
 
   Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP); // Output chain