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[RISCV] Add a generic OOO CPU #120712

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Merged
wangpc-pp merged 7 commits into from
Feb 14, 2025
Merged

[RISCV] Add a generic OOO CPU #120712

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e4edc40
[RISCV] Add a generic OOO CPU
wangpc-pp Dec 20, 2024
45cbe2d
Update target-invalid-cpu-note/riscv.c
wangpc-pp Dec 31, 2024
9a2658d
Adjust latency and remove --all-stats
wangpc-pp Jan 17, 2025
06d9ce2
Adjust branch/mul/div units
wangpc-pp Feb 6, 2025
5e13d85
Add more comments and adjust Zfh
wangpc-pp Feb 7, 2025
90d7711
Remove vector and address comments
wangpc-pp Feb 14, 2025
e731820
Fix errors after rebasing and add a release note
wangpc-pp Feb 14, 2025
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2 changes: 2 additions & 0 deletions clang/docs/ReleaseNotes.rst
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Expand Up @@ -217,6 +217,8 @@ LoongArch Support
RISC-V Support
^^^^^^^^^^^^^^

- Add support for `-mtune=generic-ooo` (a generic out-of-order model).

CUDA/HIP Language Changes
^^^^^^^^^^^^^^^^^^^^^^^^^

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2 changes: 2 additions & 0 deletions clang/test/Misc/target-invalid-cpu-note/riscv.c
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Expand Up @@ -66,6 +66,7 @@
// TUNE-RISCV32-SAME: {{^}}, syntacore-scr4-rv32
// TUNE-RISCV32-SAME: {{^}}, syntacore-scr5-rv32
// TUNE-RISCV32-SAME: {{^}}, generic
// TUNE-RISCV32-SAME: {{^}}, generic-ooo
// TUNE-RISCV32-SAME: {{^}}, rocket
// TUNE-RISCV32-SAME: {{^}}, sifive-7-series
// TUNE-RISCV32-SAME: {{$}}
Expand Down Expand Up @@ -96,6 +97,7 @@
// TUNE-RISCV64-SAME: {{^}}, veyron-v1
// TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
// TUNE-RISCV64-SAME: {{^}}, generic
// TUNE-RISCV64-SAME: {{^}}, generic-ooo
// TUNE-RISCV64-SAME: {{^}}, rocket
// TUNE-RISCV64-SAME: {{^}}, sifive-7-series
// TUNE-RISCV64-SAME: {{$}}
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCV.td
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Expand Up @@ -45,7 +45,7 @@ include "RISCVMacroFusion.td"
//===----------------------------------------------------------------------===//
// RISC-V Scheduling Models
//===----------------------------------------------------------------------===//

include "RISCVSchedGenericOOO.td"
include "RISCVSchedMIPSP8700.td"
include "RISCVSchedRocket.td"
include "RISCVSchedSiFive7.td"
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2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVProcessors.td
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Expand Up @@ -103,6 +103,8 @@ def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
// Support generic for compatibility with other targets. The triple will be used
// to change to the appropriate rv32/rv64 version.
def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo;
def GENERIC_OOO : RISCVTuneProcessorModel<"generic-ooo", GenericOOOModel>,
GenericTuneInfo;

def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
MIPSP8700Model,
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