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[llvm][aarch64] fix copypaste typo #120725

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Merged
merged 2 commits into from
Jan 2, 2025
Merged

[llvm][aarch64] fix copypaste typo #120725

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0b62717
fix typo
Dec 20, 2024
6b8dc45
add test
Dec 20, 2024
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -18396,7 +18396,7 @@ static SDValue performUADDVAddCombine(SDValue A, SelectionDAG &DAG) {
EVT VT = A.getValueType();
SDValue Op0 = A.getOperand(0);
SDValue Op1 = A.getOperand(1);
if (Op0.getOpcode() != Op0.getOpcode() ||
if (Op0.getOpcode() != Op1.getOpcode() ||
(Op0.getOpcode() != ISD::ZERO_EXTEND &&
Op0.getOpcode() != ISD::SIGN_EXTEND))
return SDValue();
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18 changes: 18 additions & 0 deletions llvm/test/CodeGen/AArch64/vecreduce-add.ll
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Expand Up @@ -72,6 +72,24 @@ entry:
ret i64 %z
}

define i64 @add_v4i32_v4i64_zsext(<4 x i32> %xi) {
; CHECK-LABEL: add_v4i32_v4i64_zsext:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ushll v1.2d, v0.2s, #0
; CHECK-NEXT: saddw2 v0.2d, v1.2d, v0.4s
; CHECK-NEXT: addp d0, v0.2d
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i32> %xi, <4 x i32> %xi, <2 x i32> <i32 0, i32 1>
%y = shufflevector <4 x i32> %xi, <4 x i32> %xi, <2 x i32> <i32 2, i32 3>
%xx = zext <2 x i32> %x to <2 x i64>
%yy = sext <2 x i32> %y to <2 x i64>
%zz = add <2 x i64> %xx, %yy
%z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %zz)
ret i64 %z
}

define i64 @add_v2i32_v2i64_zext(<2 x i32> %x) {
; CHECK-LABEL: add_v2i32_v2i64_zext:
; CHECK: // %bb.0: // %entry
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