[Hexagon] Add V79 support to compiler and assembler

clang/include/clang/Basic/BuiltinsHexagon.def

@@ -17,8 +17,10 @@
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
+#pragma push_macro("V79")
+#define V79 "v79"
 #pragma push_macro("V75")
-#define V75 "v75"
+#define V75 "v75|" V79
 #pragma push_macro("V73")
 #define V73 "v73|" V75
 #pragma push_macro("V71")
@@ -42,8 +44,10 @@
 #pragma push_macro("V5")
 #define V5 "v5|" V55
 
+#pragma push_macro("HVXV79")
+#define HVXV79 "hvxv79"
 #pragma push_macro("HVXV75")
-#define HVXV75 "hvxv75"
+#define HVXV75 "hvxv75|" HVXV79
 #pragma push_macro("HVXV73")
 #define HVXV73 "hvxv73|" HVXV75
 #pragma push_macro("HVXV71")
@@ -148,6 +152,7 @@ TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "
 #pragma pop_macro("HVXV71")
 #pragma pop_macro("HVXV73")
 #pragma pop_macro("HVXV75")
+#pragma pop_macro("HVXV79")
 
 #pragma pop_macro("V5")
 #pragma pop_macro("V55")
@@ -161,6 +166,7 @@ TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "
 #pragma pop_macro("V71")
 #pragma pop_macro("V73")
 #pragma pop_macro("V75")
+#pragma pop_macro("V79")
 
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/include/clang/Driver/Options.td

@@ -6226,6 +6226,8 @@ def mv73 : Flag<["-"], "mv73">, Group<m_hexagon_Features_Group>,
   Alias<mcpu_EQ>, AliasArgs<["hexagonv73"]>;
 def mv75 : Flag<["-"], "mv75">, Group<m_hexagon_Features_Group>,
   Alias<mcpu_EQ>, AliasArgs<["hexagonv75"]>;
+def mv79 : Flag<["-"], "mv79">, Group<m_hexagon_Features_Group>,
+  Alias<mcpu_EQ>, AliasArgs<["hexagonv79"]>;
 def mhexagon_hvx : Flag<["-"], "mhvx">, Group<m_hexagon_Features_HVX_Group>,
   HelpText<"Enable Hexagon Vector eXtensions">;
 def mhexagon_hvx_EQ : Joined<["-"], "mhvx=">,

clang/lib/Basic/Targets/Hexagon.cpp

@@ -81,6 +81,9 @@ void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
   } else if (CPU == "hexagonv75") {
     Builder.defineMacro("__HEXAGON_V75__");
     Builder.defineMacro("__HEXAGON_ARCH__", "75");
+  } else if (CPU == "hexagonv79") {
+    Builder.defineMacro("__HEXAGON_V79__");
+    Builder.defineMacro("__HEXAGON_ARCH__", "79");
   }
 
   if (hasFeature("hvx-length64b")) {
@@ -239,6 +242,7 @@ static constexpr CPUSuffix Suffixes[] = {
     {{"hexagonv68"}, {"68"}}, {{"hexagonv69"}, {"69"}},
     {{"hexagonv71"}, {"71"}}, {{"hexagonv71t"}, {"71t"}},
     {{"hexagonv73"}, {"73"}}, {{"hexagonv75"}, {"75"}},
+    {{"hexagonv79"}, {"79"}},
 };
 
 std::optional<unsigned> HexagonTargetInfo::getHexagonCPURev(StringRef Name) {

clang/test/Driver/hexagon-toolchain-elf.c

@@ -159,6 +159,13 @@
 // CHECK240: "-cc1" {{.*}} "-target-cpu" "hexagonv75"
 // CHECK240: hexagon-link{{.*}}/Inputs/hexagon_tree/Tools/bin/../target/hexagon/lib/v75/crt0
 
+// RUN: not %clang -### --target=hexagon-unknown-elf \
+// RUN:   -ccc-install-dir %S/Inputs/hexagon_tree/Tools/bin \
+// RUN:   -mcpu=hexagonv79 -fuse-ld=hexagon-link \
+// RUN:   %s 2>&1 | FileCheck -check-prefix=CHECK250 %s
+// CHECK250: "-cc1" {{.*}} "-target-cpu" "hexagonv79"
+// CHECK250: hexagon-link{{.*}}/Inputs/hexagon_tree/Tools/bin/../target/hexagon/lib/v79/crt0
+
 // -----------------------------------------------------------------------------
 // Test Linker related args
 // -----------------------------------------------------------------------------

clang/test/Misc/target-invalid-cpu-note/hexagon.c

@@ -19,4 +19,5 @@
 // CHECK-SAME: {{^}}, hexagonv71t
 // CHECK-SAME: {{^}}, hexagonv73
 // CHECK-SAME: {{^}}, hexagonv75
+// CHECK-SAME: {{^}}, hexagonv79
 // CHECK-SAME: {{$}}

clang/test/Preprocessor/hexagon-predefines.c

@@ -154,6 +154,23 @@
 // CHECK-V75HVX-128B: #define __HVX__ 1
 // CHECK-V75HVX-128B: #define __hexagon__ 1
 
+// RUN: %clang_cc1 -E -dM -triple hexagon-unknown-elf -target-cpu hexagonv79 %s\
+// RUN: | FileCheck %s -check-prefix CHECK-V79
+// CHECK-V79: #define __HEXAGON_ARCH__ 79
+// CHECK-V79: #define __HEXAGON_PHYSICAL_SLOTS__ 4
+// CHECK-V79: #define __HEXAGON_V79__ 1
+// CHECK-V79: #define __hexagon__ 1
+
+// RUN: %clang_cc1 -E -dM -triple hexagon-unknown-elf -target-cpu hexagonv79 \
+// RUN: -target-feature +hvxv79 -target-feature +hvx-length128b %s | FileCheck \
+// RUN: %s -check-prefix CHECK-V79HVX-128B
+// CHECK-V79HVX-128B: #define __HEXAGON_ARCH__ 79
+// CHECK-V79HVX-128B: #define __HEXAGON_V79__ 1
+// CHECK-V79HVX-128B: #define __HVX_ARCH__ 79
+// CHECK-V79HVX-128B: #define __HVX_LENGTH__ 128
+// CHECK-V79HVX-128B: #define __HVX__ 1
+// CHECK-V79HVX-128B: #define __hexagon__ 1
+
 // RUN: %clang_cc1 -E -dM -triple hexagon-unknown-elf -target-cpu hexagonv67 \
 // RUN: -target-feature +hvxv67 -target-feature +hvx-length128b %s | FileCheck \
 // RUN: %s -check-prefix CHECK-ELF

llvm/include/llvm/BinaryFormat/ELF.h

@@ -630,6 +630,7 @@ enum {
   EF_HEXAGON_MACH_V71T = 0x00008071, // Hexagon V71T
   EF_HEXAGON_MACH_V73 = 0x00000073,  // Hexagon V73
   EF_HEXAGON_MACH_V75 = 0x00000075,  // Hexagon V75
+  EF_HEXAGON_MACH_V79 = 0x00000079,  // Hexagon V79
   EF_HEXAGON_MACH = 0x000003ff,      // Hexagon V..
 
   // Highest ISA version flags
@@ -650,6 +651,7 @@ enum {
   EF_HEXAGON_ISA_V71 = 0x00000071,  // Hexagon V71 ISA
   EF_HEXAGON_ISA_V73 = 0x00000073,  // Hexagon V73 ISA
   EF_HEXAGON_ISA_V75 = 0x00000075,  // Hexagon V75 ISA
+  EF_HEXAGON_ISA_V79 = 0x00000079,  // Hexagon V79 ISA
   EF_HEXAGON_ISA = 0x000003ff,      // Hexagon V.. ISA
 };
 

llvm/include/llvm/IR/IntrinsicsHexagonDep.td

@@ -6705,3 +6705,130 @@ Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_sf_bf">;
 def int_hexagon_V6_vsub_sf_bf_128B :
 Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_sf_bf_128B">;
 
+// V79 HVX Instructions.
+
+def int_hexagon_V6_get_qfext :
+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_get_qfext">;
+
+def int_hexagon_V6_get_qfext_128B :
+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_get_qfext_128B">;
+
+def int_hexagon_V6_get_qfext_oracc :
+Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_get_qfext_oracc">;
+
+def int_hexagon_V6_get_qfext_oracc_128B :
+Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_get_qfext_oracc_128B">;
+
+def int_hexagon_V6_set_qfext :
+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_set_qfext">;
+
+def int_hexagon_V6_set_qfext_128B :
+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_set_qfext_128B">;
+
+def int_hexagon_V6_vabs_f8 :
+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabs_f8">;
+
+def int_hexagon_V6_vabs_f8_128B :
+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabs_f8_128B">;
+
+def int_hexagon_V6_vadd_hf_f8 :
+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadd_hf_f8">;
+
+def int_hexagon_V6_vadd_hf_f8_128B :
+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadd_hf_f8_128B">;
+
+def int_hexagon_V6_vcvt2_b_hf :
+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt2_b_hf">;
+
+def int_hexagon_V6_vcvt2_b_hf_128B :
+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt2_b_hf_128B">;
+
+def int_hexagon_V6_vcvt2_hf_b :
+Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt2_hf_b">;
+
+def int_hexagon_V6_vcvt2_hf_b_128B :
+Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt2_hf_b_128B">;
+
+def int_hexagon_V6_vcvt2_hf_ub :
+Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt2_hf_ub">;
+
+def int_hexagon_V6_vcvt2_hf_ub_128B :
+Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt2_hf_ub_128B">;
+
+def int_hexagon_V6_vcvt2_ub_hf :
+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt2_ub_hf">;
+
+def int_hexagon_V6_vcvt2_ub_hf_128B :
+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt2_ub_hf_128B">;
+
+def int_hexagon_V6_vcvt_f8_hf :
+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcvt_f8_hf">;
+
+def int_hexagon_V6_vcvt_f8_hf_128B :
+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcvt_f8_hf_128B">;
+
+def int_hexagon_V6_vcvt_hf_f8 :
+Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vcvt_hf_f8">;
+
+def int_hexagon_V6_vcvt_hf_f8_128B :
+Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vcvt_hf_f8_128B">;
+
+def int_hexagon_V6_vfmax_f8 :
+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmax_f8">;
+
+def int_hexagon_V6_vfmax_f8_128B :
+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmax_f8_128B">;
+
+def int_hexagon_V6_vfmin_f8 :
+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vfmin_f8">;
+
+def int_hexagon_V6_vfmin_f8_128B :
+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vfmin_f8_128B">;
+
+def int_hexagon_V6_vfneg_f8 :
+Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vfneg_f8">;
+
+def int_hexagon_V6_vfneg_f8_128B :
+Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vfneg_f8_128B">;
+
+def int_hexagon_V6_vmerge_qf :
+Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmerge_qf">;
+
+def int_hexagon_V6_vmerge_qf_128B :
+Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmerge_qf_128B">;
+
+def int_hexagon_V6_vmpy_hf_f8 :
+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_hf_f8">;
+
+def int_hexagon_V6_vmpy_hf_f8_128B :
+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_hf_f8_128B">;
+
+def int_hexagon_V6_vmpy_hf_f8_acc :
+Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpy_hf_f8_acc">;
+
+def int_hexagon_V6_vmpy_hf_f8_acc_128B :
+Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpy_hf_f8_acc_128B">;
+
+def int_hexagon_V6_vmpy_rt_hf :
+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpy_rt_hf">;
+
+def int_hexagon_V6_vmpy_rt_hf_128B :
+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpy_rt_hf_128B">;
+
+def int_hexagon_V6_vmpy_rt_qf16 :
+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpy_rt_qf16">;
+
+def int_hexagon_V6_vmpy_rt_qf16_128B :
+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpy_rt_qf16_128B">;
+
+def int_hexagon_V6_vmpy_rt_sf :
+Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpy_rt_sf">;
+
+def int_hexagon_V6_vmpy_rt_sf_128B :
+Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpy_rt_sf_128B">;
+
+def int_hexagon_V6_vsub_hf_f8 :
+Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsub_hf_f8">;
+
+def int_hexagon_V6_vsub_hf_f8_128B :
+Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsub_hf_f8_128B">;

llvm/lib/Target/Hexagon/Hexagon.td

@@ -73,6 +73,12 @@ def ExtensionHVXV75: SubtargetFeature<"hvxv75", "HexagonHVXVersion",
        ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71,
        ExtensionHVXV73]>;
 
+def ExtensionHVXV79: SubtargetFeature<"hvxv79", "HexagonHVXVersion",
+      "Hexagon::ArchEnum::V79", "Hexagon HVX instructions",
+      [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
+       ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71,
+       ExtensionHVXV73, ExtensionHVXV75]>;
+
 def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",
       "true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;
 def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps",
@@ -145,6 +151,8 @@ def UseHVXV73          : Predicate<"HST->useHVXV73Ops()">,
                          AssemblerPredicate<(all_of ExtensionHVXV73)>;
 def UseHVXV75          : Predicate<"HST->useHVXV75Ops()">,
                          AssemblerPredicate<(all_of ExtensionHVXV75)>;
+def UseHVXV79          : Predicate<"HST->useHVXV79Ops()">,
+                         AssemblerPredicate<(all_of ExtensionHVXV79)>;
 def UseAudio           : Predicate<"HST->useAudioOps()">,
                          AssemblerPredicate<(all_of ExtensionAudio)>;
 def UseZReg            : Predicate<"HST->useZRegOps()">,
@@ -475,6 +483,11 @@ def : Proc<"hexagonv75", HexagonModelV75,
            ArchV68, ArchV69, ArchV71, ArchV73, ArchV75, FeatureCompound,
            FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,
            FeatureNVS, FeaturePackets, FeatureSmallData]>;
+def : Proc<"hexagonv79", HexagonModelV79,
+           [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67,
+           ArchV68, ArchV69, ArchV71, ArchV73, ArchV75, ArchV79,
+           FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops,
+           FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>;
 
 // Need to update the correct features for tiny core.
 // Disable NewValueJumps since the packetizer is unable to handle a packet with

llvm/lib/Target/Hexagon/HexagonDepArch.h

@@ -28,7 +28,8 @@ enum class ArchEnum {
   V69,
   V71,
   V73,
-  V75
+  V75,
+  V79
 };
 
 inline std::optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
@@ -48,6 +49,7 @@ inline std::optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
       .Case("hexagonv71t", Hexagon::ArchEnum::V71)
       .Case("hexagonv73", Hexagon::ArchEnum::V73)
       .Case("hexagonv75", Hexagon::ArchEnum::V75)
+      .Case("hexagonv79", Hexagon::ArchEnum::V79)
       .Default(std::nullopt);
 }
 } // namespace Hexagon

llvm/lib/Target/Hexagon/HexagonDepArch.td

@@ -32,3 +32,5 @@ def ArchV73: SubtargetFeature<"v73", "HexagonArchVersion", "Hexagon::ArchEnum::V
 def HasV73 : Predicate<"HST->hasV73Ops()">, AssemblerPredicate<(all_of ArchV73)>;
 def ArchV75: SubtargetFeature<"v75", "HexagonArchVersion", "Hexagon::ArchEnum::V75", "Enable Hexagon V75 architecture">;
 def HasV75 : Predicate<"HST->hasV75Ops()">, AssemblerPredicate<(all_of ArchV75)>;
+def ArchV79: SubtargetFeature<"v79", "HexagonArchVersion", "Hexagon::ArchEnum::V79", "Enable Hexagon V79 architecture">;
+def HasV79 : Predicate<"HST->hasV79Ops()">, AssemblerPredicate<(all_of ArchV79)>;