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[RISCV] GISel custom lowering for G_ADD/G_SUB #121587

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Merged
merged 3 commits into from
Jan 8, 2025
Merged

[RISCV] GISel custom lowering for G_ADD/G_SUB #121587

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bd0a8fb
[RISCV] GISel custom lowering for addiw
lquinn2015 Jan 3, 2025
c8b4155
[RISCV] Optimization expanded to cover G_SUB/subw as well
lquinn2015 Jan 3, 2025
42e32d0
[RISCV] reduce usage of createGenericVirtualREgister
lquinn2015 Jan 6, 2025
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29 changes: 28 additions & 1 deletion llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
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Expand Up @@ -21,6 +21,7 @@
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/ValueTypes.h"
Expand Down Expand Up @@ -132,7 +133,14 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)

auto PtrVecTys = {nxv1p0, nxv2p0, nxv4p0, nxv8p0, nxv16p0};

getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR})
getActionDefinitionsBuilder({G_ADD, G_SUB})
.legalFor({sXLen})
.legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))
.customFor(ST.is64Bit(), {s32})
.widenScalarToNextPow2(0)
.clampScalar(0, sXLen, sXLen);

getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
.legalFor({sXLen})
.legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))
.widenScalarToNextPow2(0)
Expand Down Expand Up @@ -1330,6 +1338,25 @@ bool RISCVLegalizerInfo::legalizeCustom(
return true;
return Helper.lowerConstant(MI);
}
case TargetOpcode::G_SUB:
case TargetOpcode::G_ADD: {
Helper.Observer.changingInstr(MI);
Helper.widenScalarSrc(MI, LLT::scalar(64), 1, TargetOpcode::G_ANYEXT);
Helper.widenScalarSrc(MI, LLT::scalar(64), 2, TargetOpcode::G_ANYEXT);

Register DstALU = MRI.createGenericVirtualRegister(sXLen);
Register DstSext = MRI.createGenericVirtualRegister(sXLen);
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@arsenm arsenm Jan 4, 2025

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You should very rarely use createGenericVirtualRegister calls, fold this into auto DstSext = buildSextInReg(sXLen) etc

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@lquinn2015 lquinn2015 Jan 4, 2025

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I am confused at to which API your referencing to. I didn't see a buildSextInReg that produces that pattern out and without that I don't know how to rewrite everything

I need to match this this pattern

%3 = G_ADD %0, %2

into

%4 = AnyExt %0
%5 = AnyExt %2
%6 = G_ADD %5, %4
%7 = G_SExtInReg %6
%3 = G_Trunc %8

But i don't have that %6 or %5 until after the final call so I don't know which API to use. Should i make another buildSextInReg that i build myself in the code gen modules??

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@topperc topperc Jan 4, 2025

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I think Matt meant buildSExtInReg(sXLen, DstALU, 32). If you pass an LLT as the first operand, it will automatically create the virtual register.

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@lquinn2015 lquinn2015 Jan 6, 2025 •
edited
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From a being new perspective its is a little hard to understand from the headers what DstOp is coercionable but i do like being able to just i give a LLT for the buildSExtInReg. Spotting the union type for it is tricky. I tried to do the same for the SrcOp naively but that didn't seem to work the same. Maybe its possible but I am not reading the correct header for it!

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@arsenm arsenm Jan 7, 2025

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It doesn't make sense to use an LLT in the SrcOp case because then you'd be creating an undefined use


MachineOperand &MO = MI.getOperand(0);
MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
MIRBuilder.buildSExtInReg(DstSext, DstALU, 32);

MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {MO}, {DstSext});
MO.setReg(DstALU);

Helper.Observer.changedInstr(MI);
return true;
}
case TargetOpcode::G_SEXT_INREG: {
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
int64_t SizeInBits = MI.getOperand(2).getImm();
Expand Down
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ define i32 @add_positive_low_bound_reject(i32 %a) nounwind {
;
; RV64I-LABEL: add_positive_low_bound_reject:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, 2047
; RV64I-NEXT: addiw a0, a0, 2047
; RV64I-NEXT: ret
%1 = add i32 %a, 2047
ret i32 %1
Expand All @@ -30,7 +30,7 @@ define i32 @add_positive_low_bound_accept(i32 %a) nounwind {
; RV64I-LABEL: add_positive_low_bound_accept:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, 2047
; RV64I-NEXT: addi a0, a0, 1
; RV64I-NEXT: addiw a0, a0, 1
; RV64I-NEXT: ret
%1 = add i32 %a, 2048
ret i32 %1
Expand All @@ -46,7 +46,7 @@ define i32 @add_positive_high_bound_accept(i32 %a) nounwind {
; RV64I-LABEL: add_positive_high_bound_accept:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, 2047
; RV64I-NEXT: addi a0, a0, 2047
; RV64I-NEXT: addiw a0, a0, 2047
; RV64I-NEXT: ret
%1 = add i32 %a, 4094
ret i32 %1
Expand All @@ -63,8 +63,8 @@ define i32 @add_positive_high_bound_reject(i32 %a) nounwind {
; RV64I-LABEL: add_positive_high_bound_reject:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
%1 = add i32 %a, 4095
ret i32 %1
Expand All @@ -78,7 +78,7 @@ define i32 @add_negative_high_bound_reject(i32 %a) nounwind {
;
; RV64I-LABEL: add_negative_high_bound_reject:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, -2048
; RV64I-NEXT: addiw a0, a0, -2048
; RV64I-NEXT: ret
%1 = add i32 %a, -2048
ret i32 %1
Expand All @@ -94,7 +94,7 @@ define i32 @add_negative_high_bound_accept(i32 %a) nounwind {
; RV64I-LABEL: add_negative_high_bound_accept:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, -2048
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: ret
%1 = add i32 %a, -2049
ret i32 %1
Expand All @@ -110,7 +110,7 @@ define i32 @add_negative_low_bound_accept(i32 %a) nounwind {
; RV64I-LABEL: add_negative_low_bound_accept:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, -2048
; RV64I-NEXT: addi a0, a0, -2048
; RV64I-NEXT: addiw a0, a0, -2048
; RV64I-NEXT: ret
%1 = add i32 %a, -4096
ret i32 %1
Expand All @@ -127,8 +127,8 @@ define i32 @add_negative_low_bound_reject(i32 %a) nounwind {
; RV64I-LABEL: add_negative_low_bound_reject:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
%1 = add i32 %a, -4097
ret i32 %1
Expand All @@ -144,7 +144,7 @@ define i32 @add32_accept(i32 %a) nounwind {
; RV64I-LABEL: add32_accept:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, 2047
; RV64I-NEXT: addi a0, a0, 952
; RV64I-NEXT: addiw a0, a0, 952
; RV64I-NEXT: ret
%1 = add i32 %a, 2999
ret i32 %1
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
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Expand Up @@ -37,7 +37,7 @@ define i32 @add_i8_signext_i32(i8 %a, i8 %b) {
; RV64IM-NEXT: slli a1, a1, 56
; RV64IM-NEXT: srai a0, a0, 56
; RV64IM-NEXT: srai a1, a1, 56
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret
entry:
%0 = sext i8 %a to i32
Expand All @@ -58,7 +58,7 @@ define i32 @add_i8_zeroext_i32(i8 %a, i8 %b) {
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: andi a0, a0, 255
; RV64IM-NEXT: andi a1, a1, 255
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret
entry:
%0 = zext i8 %a to i32
Expand All @@ -78,7 +78,7 @@ define i32 @add_i32(i32 %a, i32 %b) {
;
; RV64IM-LABEL: add_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret
entry:
%0 = add i32 %a, %b
Expand All @@ -93,7 +93,7 @@ define i32 @addi_i32(i32 %a) {
;
; RV64IM-LABEL: addi_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: addi a0, a0, 1234
; RV64IM-NEXT: addiw a0, a0, 1234
; RV64IM-NEXT: ret
entry:
%0 = add i32 %a, 1234
Expand All @@ -108,7 +108,7 @@ define i32 @sub_i32(i32 %a, i32 %b) {
;
; RV64IM-LABEL: sub_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: sub a0, a0, a1
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: ret
entry:
%0 = sub i32 %a, %b
Expand All @@ -123,7 +123,7 @@ define i32 @subi_i32(i32 %a) {
;
; RV64IM-LABEL: subi_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: addi a0, a0, -1234
; RV64IM-NEXT: addiw a0, a0, -1234
; RV64IM-NEXT: ret
entry:
%0 = sub i32 %a, 1234
Expand All @@ -138,7 +138,7 @@ define i32 @neg_i32(i32 %a) {
;
; RV64IM-LABEL: neg_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: neg a0, a0
; RV64IM-NEXT: negw a0, a0
; RV64IM-NEXT: ret
entry:
%0 = sub i32 0, %a
Expand Down
3 changes: 2 additions & 1 deletion llvm/test/CodeGen/RISCV/GlobalISel/combine.ll
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Expand Up @@ -21,6 +21,7 @@ define i32 @constant_to_rhs(i32 %x) {
; RV64-O0-NEXT: mv a1, a0
; RV64-O0-NEXT: li a0, 1
; RV64-O0-NEXT: add a0, a0, a1
; RV64-O0-NEXT: sext.w a0, a0
; RV64-O0-NEXT: ret
;
; RV32-OPT-LABEL: constant_to_rhs:
Expand All @@ -30,7 +31,7 @@ define i32 @constant_to_rhs(i32 %x) {
;
; RV64-OPT-LABEL: constant_to_rhs:
; RV64-OPT: # %bb.0:
; RV64-OPT-NEXT: addi a0, a0, 1
; RV64-OPT-NEXT: addiw a0, a0, 1
; RV64-OPT-NEXT: ret
%a = add i32 1, %x
ret i32 %a
Expand Down
61 changes: 41 additions & 20 deletions llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
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Expand Up @@ -96,12 +96,19 @@ define ptr @freeze_ptr(ptr %x) {
%struct.T = type { i32, i32 }

define i32 @freeze_struct(ptr %p) {
; CHECK-LABEL: freeze_struct:
; CHECK: # %bb.0:
; CHECK-NEXT: lw a1, 0(a0)
; CHECK-NEXT: lw a0, 4(a0)
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: ret
; RV32-LABEL: freeze_struct:
; RV32: # %bb.0:
; RV32-NEXT: lw a1, 0(a0)
; RV32-NEXT: lw a0, 4(a0)
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: freeze_struct:
; RV64: # %bb.0:
; RV64-NEXT: lw a1, 0(a0)
; RV64-NEXT: lw a0, 4(a0)
; RV64-NEXT: addw a0, a1, a0
; RV64-NEXT: ret
%s = load %struct.T, ptr %p
%y1 = freeze %struct.T %s
%v1 = extractvalue %struct.T %y1, 0
Expand All @@ -111,12 +118,19 @@ define i32 @freeze_struct(ptr %p) {
}

define i32 @freeze_anonstruct(ptr %p) {
; CHECK-LABEL: freeze_anonstruct:
; CHECK: # %bb.0:
; CHECK-NEXT: lw a1, 0(a0)
; CHECK-NEXT: lw a0, 4(a0)
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: ret
; RV32-LABEL: freeze_anonstruct:
; RV32: # %bb.0:
; RV32-NEXT: lw a1, 0(a0)
; RV32-NEXT: lw a0, 4(a0)
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: freeze_anonstruct:
; RV64: # %bb.0:
; RV64-NEXT: lw a1, 0(a0)
; RV64-NEXT: lw a0, 4(a0)
; RV64-NEXT: addw a0, a1, a0
; RV64-NEXT: ret
%s = load {i32, i32}, ptr %p
%y1 = freeze {i32, i32} %s
%v1 = extractvalue {i32, i32} %y1, 0
Expand All @@ -141,7 +155,7 @@ define i32 @freeze_anonstruct2(ptr %p) {
; RV64-NEXT: lw a0, 0(a0)
; RV64-NEXT: slli a1, a1, 48
; RV64-NEXT: srli a1, a1, 48
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: addw a0, a0, a1
; RV64-NEXT: ret
%s = load {i32, i16}, ptr %p
%y1 = freeze {i32, i16} %s
Expand All @@ -168,7 +182,7 @@ define i32 @freeze_anonstruct2_sext(ptr %p) {
; RV64-NEXT: lw a0, 0(a0)
; RV64-NEXT: slli a1, a1, 48
; RV64-NEXT: srai a1, a1, 48
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: addw a0, a0, a1
; RV64-NEXT: ret
%s = load {i32, i16}, ptr %p
%y1 = freeze {i32, i16} %s
Expand All @@ -180,12 +194,19 @@ define i32 @freeze_anonstruct2_sext(ptr %p) {
}

define i32 @freeze_array(ptr %p) nounwind {
; CHECK-LABEL: freeze_array:
; CHECK: # %bb.0:
; CHECK-NEXT: lw a1, 0(a0)
; CHECK-NEXT: lw a0, 4(a0)
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: ret
; RV32-LABEL: freeze_array:
; RV32: # %bb.0:
; RV32-NEXT: lw a1, 0(a0)
; RV32-NEXT: lw a0, 4(a0)
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: freeze_array:
; RV64: # %bb.0:
; RV64-NEXT: lw a1, 0(a0)
; RV64-NEXT: lw a0, 4(a0)
; RV64-NEXT: addw a0, a1, a0
; RV64-NEXT: ret
%s = load [2 x i32], ptr %p
%y1 = freeze [2 x i32] %s
%v1 = extractvalue [2 x i32] %y1, 0
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll
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Expand Up @@ -98,7 +98,7 @@ define i32 @abs32(i32 %x) {
; RV64I-LABEL: abs32:
; RV64I: # %bb.0:
; RV64I-NEXT: sraiw a1, a0, 31
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ret
;
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
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Expand Up @@ -23,7 +23,7 @@
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_SUB (opcode [[SUB_OPC:[0-9]+]]): 1 type index, 0 imm indices
# DEBUG-NEXT: .. opcode [[SUB_OPC]] is aliased to [[ADD_OPC]]
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
Expand Down Expand Up @@ -59,7 +59,6 @@
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_AND (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
Expand Down
7 changes: 4 additions & 3 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir
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Expand Up @@ -86,9 +86,10 @@ body: |
; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ASSERT_SEXT]], [[C]](s64)
; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_SEXT]], [[ASHR]]
; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]]
; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[XOR]], 32
; RV64I-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32
; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[SEXT_INREG]], [[ASHR]]
; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[XOR]], 32
; RV64I-NEXT: $x10 = COPY [[SEXT_INREG1]](s64)
; RV64I-NEXT: PseudoRET implicit $x10
;
; RV64ZBB-LABEL: name: abs_i32
Expand Down
3 changes: 2 additions & 1 deletion llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir
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Expand Up @@ -69,7 +69,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32
; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11
Expand Down
11 changes: 6 additions & 5 deletions llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir
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Expand Up @@ -339,7 +339,7 @@ body: |
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
; CHECK-NEXT: $x11 = COPY [[ICMP]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
%2:_(s64) = COPY $x10
Expand Down Expand Up @@ -454,10 +454,11 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]]
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
; CHECK-NEXT: $x10 = COPY [[SUB]](s64)
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 32
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG1]](s64), [[SEXT_INREG2]]
; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
; CHECK-NEXT: $x11 = COPY [[ICMP]](s64)
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
%2:_(s64) = COPY $x10
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3 changes: 2 additions & 1 deletion llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir
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Expand Up @@ -145,7 +145,8 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -64769
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]]
; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32
; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = G_CONSTANT i32 -64769
%1:_(s64) = COPY $x10
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