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[RISCV] Support [mh]edelegh CSRs #121634

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Merged
merged 8 commits into from
Feb 16, 2025
Merged

[RISCV] Support [mh]edelegh CSRs #121634

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bcdf964
Update RISCVSystemOperands.td
dong-miao Jan 4, 2025
30e3fbe
Update rv32-hypervisor-csr-names.s
dong-miao Jan 4, 2025
e41e745
Update rv32-machine-csr-names.s
dong-miao Jan 4, 2025
ea2c1af
Update RISCVSystemOperands.td
dong-miao Jan 5, 2025
6b074f3
Update rv32-only-csr-names.s
dong-miao Jan 5, 2025
f77d8e3
Update RISCVSystemOperands.td
dong-miao Jan 5, 2025
58a1fe2
Merge branch 'main' into main
dong-miao Jan 13, 2025
17b994b
Merge branch 'main' into main
dong-miao Feb 12, 2025
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6 changes: 5 additions & 1 deletion llvm/lib/Target/RISCV/RISCVSystemOperands.td
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Original file line number Diff line number Diff line change
Expand Up @@ -148,6 +148,8 @@ def : SysReg<"hideleg", 0x603>;
def : SysReg<"hie", 0x604>;
def : SysReg<"hcounteren", 0x606>;
def : SysReg<"hgeie", 0x607>;
let isRV32Only = 1 in
def : SysReg<"hedelegh", 0x612>;

//===----------------------------------------------------------------------===//
// Hypervisor Trap Handling
Expand Down Expand Up @@ -224,8 +226,10 @@ def : SysReg<"mideleg", 0x303>;
def : SysReg<"mie", 0x304>;
def : SysReg<"mtvec", 0x305>;
def : SysReg<"mcounteren", 0x306>;
let isRV32Only = 1 in
let isRV32Only = 1 in {
def : SysReg<"mstatush", 0x310>;
def : SysReg<"medelegh", 0x312>;
} // isRV32Only

//===----------------------------------------------------------------------===//
// Machine Trap Handling
Expand Down
18 changes: 18 additions & 0 deletions llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
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Expand Up @@ -219,3 +219,21 @@ csrrs t2, 0x214, zero
csrrs t1, vsiph, zero
# uimm12
csrrs t2, 0x254, zero

##################################
# Hypervisor Trap Setup
##################################

# hedelegh
# name
# CHECK-INST: csrrs t1, hedelegh, zero
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61]
# CHECK-INST-ALIAS: csrr t1, hedelegh
# uimm12
# CHECK-INST: csrrs t2, hedelegh, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61]
# CHECK-INST-ALIAS: csrr t2, hedelegh
# name
csrrs t1, hedelegh, zero
# uimm12
csrrs t2, 0x612, zero
14 changes: 14 additions & 0 deletions llvm/test/MC/RISCV/rv32-machine-csr-names.s
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Expand Up @@ -22,6 +22,20 @@ csrrs t1, mstatush, zero
# uimm12
csrrs t2, 0x310, zero

# medelegh
# name
# CHECK-INST: csrrs t1, medelegh, zero
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31]
# CHECK-INST-ALIAS: csrr t1, medelegh
# uimm12
# CHECK-INST: csrrs t2, medelegh, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31]
# CHECK-INST-ALIAS: csrr t2, medelegh
# name
csrrs t1, medelegh, zero
# uimm12
csrrs t2, 0x312, zero

#########################
# Machine Configuration
#########################
Expand Down
4 changes: 4 additions & 0 deletions llvm/test/MC/RISCV/rv32-only-csr-names.s
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Expand Up @@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system registe

csrrs t1, htimedeltah, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'htimedeltah' is RV32 only

csrrs t1, hedelegh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'hedelegh' is RV32 only

csrrs t1, mstatush, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mstatush' is RV32 only

csrrs t1, menvcfgh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'menvcfgh' is RV32 only

csrrs t1, mseccfgh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'mseccfgh' is RV32 only

csrrs t1, medelegh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'medelegh' is RV32 only

csrrs t1, pmpcfg1, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'pmpcfg1' is RV32 only
csrrs t1, pmpcfg3, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'pmpcfg3' is RV32 only
csrrs t1, pmpcfg5, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register 'pmpcfg5' is RV32 only
Expand Down
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