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[TableGen][GlobalISel] Reorder atomic predicate to preserve the order #121806
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55 changes: 55 additions & 0 deletions
55
llvm/test/TableGen/GlobalISelEmitter/predicated-pattern-order.td
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,55 @@ | ||
| // RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../../include -I %p/../Common %s | FileCheck %s | ||
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| include "llvm/Target/Target.td" | ||
| include "GlobalISelEmitterCommon.td" | ||
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| // Check that IPM_GenericPredicate doesn't influence the final order of patterns. | ||
| // https://github.com/llvm/llvm-project/issues/121446 | ||
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| def aligned_store: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{ | ||
| return true; | ||
| }]>{ | ||
| let GISelPredicateCode = [{ return true; }]; | ||
| } | ||
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| // CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(45), // Rule ID 0 // | ||
| // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, | ||
| // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_STORE), | ||
| // CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, | ||
| // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, | ||
| // CHECK-NEXT: // MIs[0] src0 | ||
| // CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, | ||
| // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), | ||
| // CHECK-NEXT: // MIs[0] src1 | ||
| // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, | ||
| // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), | ||
| // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_store), | ||
| // CHECK-NEXT: // (st GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_aligned_store>> => (MOVALIGNED GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1) | ||
| // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVALIGNED), | ||
| // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, | ||
| // CHECK-NEXT: // GIR_Coverage, 0, | ||
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| // CHECK: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(86), // Rule ID 1 // | ||
| // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, | ||
| // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_STORE), | ||
| // CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, | ||
| // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, | ||
| // CHECK-NEXT: // MIs[0] src0 | ||
| // CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, | ||
| // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), | ||
| // CHECK-NEXT: // MIs[0] src1 | ||
| // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, | ||
| // CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), | ||
| // CHECK-NEXT: // (st GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (MOVUNALIGNED GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1) | ||
| // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVUNALIGNED), | ||
| // CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, | ||
| // CHECK-NEXT: // GIR_Coverage, 1, | ||
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| def MOVALIGNED : I<(outs), (ins GPR32:$src0, GPR32:$src1), | ||
| [(aligned_store GPR32:$src0, GPR32:$src1)]>; | ||
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| def MOVUNALIGNED : I<(outs), (ins GPR32:$src0, GPR32:$src1), | ||
| [(store GPR32:$src0, GPR32:$src1)]>; | ||
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