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[NFC] Make AMDGPUCombinerHelper methods const #121903

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Merged
merged 2 commits into from
Jan 10, 2025
Merged

[NFC] Make AMDGPUCombinerHelper methods const #121903

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2da670a
[NFC] Make AMDGPUCombinerHelper methods const
paulhuggett Jan 7, 2025
5e9eefe
We can now make the Helper member const.
paulhuggett Jan 10, 2025
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10 changes: 5 additions & 5 deletions llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -197,7 +197,7 @@ static unsigned inverseMinMax(unsigned Opc) {
}

bool AMDGPUCombinerHelper::matchFoldableFneg(MachineInstr &MI,
MachineInstr *&MatchInfo) {
MachineInstr *&MatchInfo) const {
Register Src = MI.getOperand(1).getReg();
MatchInfo = MRI.getVRegDef(Src);

Expand Down Expand Up @@ -266,7 +266,7 @@ bool AMDGPUCombinerHelper::matchFoldableFneg(MachineInstr &MI,
}

void AMDGPUCombinerHelper::applyFoldableFneg(MachineInstr &MI,
MachineInstr *&MatchInfo) {
MachineInstr *&MatchInfo) const {
// Transform:
// %A = inst %Op1, ...
// %B = fneg %A
Expand Down Expand Up @@ -425,7 +425,7 @@ static bool isFPExtFromF16OrConst(const MachineRegisterInfo &MRI,
bool AMDGPUCombinerHelper::matchExpandPromotedF16FMed3(MachineInstr &MI,
Register Src0,
Register Src1,
Register Src2) {
Register Src2) const {
assert(MI.getOpcode() == TargetOpcode::G_FPTRUNC);
Register SrcReg = MI.getOperand(1).getReg();
if (!MRI.hasOneNonDBGUse(SrcReg) || MRI.getType(SrcReg) != LLT::scalar(32))
Expand All @@ -438,7 +438,7 @@ bool AMDGPUCombinerHelper::matchExpandPromotedF16FMed3(MachineInstr &MI,
void AMDGPUCombinerHelper::applyExpandPromotedF16FMed3(MachineInstr &MI,
Register Src0,
Register Src1,
Register Src2) {
Register Src2) const {
// We expect fptrunc (fpext x) to fold out, and to constant fold any constant
// sources.
Src0 = Builder.buildFPTrunc(LLT::scalar(16), Src0).getReg(0);
Expand All @@ -455,7 +455,7 @@ void AMDGPUCombinerHelper::applyExpandPromotedF16FMed3(MachineInstr &MI,

bool AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp(
MachineInstr &MI, MachineInstr &Sel,
std::function<void(MachineIRBuilder &)> &MatchInfo) {
std::function<void(MachineIRBuilder &)> &MatchInfo) const {
assert(MI.getOpcode() == TargetOpcode::G_FMUL);
assert(Sel.getOpcode() == TargetOpcode::G_SELECT);
assert(MI.getOperand(2).getReg() == Sel.getOperand(0).getReg());
Expand Down
10 changes: 5 additions & 5 deletions llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h
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Original file line number Diff line number Diff line change
Expand Up @@ -32,17 +32,17 @@ class AMDGPUCombinerHelper : public CombinerHelper {
MachineDominatorTree *MDT, const LegalizerInfo *LI,
const GCNSubtarget &STI);

bool matchFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo);
void applyFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo);
bool matchFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo) const;
void applyFoldableFneg(MachineInstr &MI, MachineInstr *&MatchInfo) const;

bool matchExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
Register Src1, Register Src2);
Register Src1, Register Src2) const;
void applyExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
Register Src1, Register Src2);
Register Src1, Register Src2) const;

bool matchCombineFmulWithSelectToFldexp(
MachineInstr &MI, MachineInstr &Sel,
std::function<void(MachineIRBuilder &)> &MatchInfo);
std::function<void(MachineIRBuilder &)> &MatchInfo) const;
};

} // namespace llvm
Expand Down
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