Skip to content

[RISCV] Update the latencies of MUL and CPOP in SiFive P400 scheduling model #122007

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jan 7, 2025
Merged

[RISCV] Update the latencies of MUL and CPOP in SiFive P400 scheduling model #122007

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -182,7 +182,7 @@ def P400WriteCMOV : SchedWriteRes<[SiFiveP400Branch, SiFiveP400IEXQ1]> {
}
def : InstRW<[P400WriteCMOV], (instrs PseudoCCMOVGPRNoX0)>;

let Latency = 3 in {
let Latency = 2 in {
// Integer multiplication
def : WriteRes<WriteIMul, [SiFiveP400MulDiv]>;
def : WriteRes<WriteIMul32, [SiFiveP400MulDiv]>;
Expand Down
60 changes: 60 additions & 0 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveP400/mul-cpop.s
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,60 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p470 -iterations=1 < %s | FileCheck %s

mul s6, s6, s7

mulw s4, s4, a2

cpop t1, t1

cpopw t2, t2

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 4
# CHECK-NEXT: Total Cycles: 8
# CHECK-NEXT: Total uOps: 4

# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.50
# CHECK-NEXT: IPC: 0.50
# CHECK-NEXT: Block RThroughput: 4.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 2 1.00 mul s6, s6, s7
# CHECK-NEXT: 1 2 1.00 mulw s4, s4, a2
# CHECK-NEXT: 1 2 1.00 cpop t1, t1
# CHECK-NEXT: 1 2 1.00 cpopw t2, t2

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFiveP400Div
# CHECK-NEXT: [1] - SiFiveP400FEXQ0
# CHECK-NEXT: [2] - SiFiveP400FloatDiv
# CHECK-NEXT: [3] - SiFiveP400IEXQ0
# CHECK-NEXT: [4] - SiFiveP400IEXQ1
# CHECK-NEXT: [5] - SiFiveP400IEXQ2
# CHECK-NEXT: [6] - SiFiveP400Load
# CHECK-NEXT: [7] - SiFiveP400Store
# CHECK-NEXT: [8] - SiFiveP400VDiv
# CHECK-NEXT: [9] - SiFiveP400VEXQ0
# CHECK-NEXT: [10] - SiFiveP400VFloatDiv
# CHECK-NEXT: [11] - SiFiveP400VLD
# CHECK-NEXT: [12] - SiFiveP400VST

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
# CHECK-NEXT: - - - - - 4.00 - - - - - - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
# CHECK-NEXT: - - - - - 1.00 - - - - - - - mul s6, s6, s7
# CHECK-NEXT: - - - - - 1.00 - - - - - - - mulw s4, s4, a2
# CHECK-NEXT: - - - - - 1.00 - - - - - - - cpop t1, t1
# CHECK-NEXT: - - - - - 1.00 - - - - - - - cpopw t2, t2
Loading