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[RISCV][VLOPT] Add mask load to isSupported and getOperandInfo #122030

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Merged
merged 2 commits into from
Jan 8, 2025
Merged

[RISCV][VLOPT] Add mask load to isSupported and getOperandInfo #122030

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e9069db
[RISCV][VLOPT] Add masked load to isSupported and getOperandInfo
michaelmaitland Jan 7, 2025
889cf19
fixup! add vsm tests
michaelmaitland Jan 8, 2025
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4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -257,6 +257,9 @@ static OperandInfo getOperandInfo(const MachineOperand &MO,
// Vector Unit-Stride Instructions
// Vector Strided Instructions
/// Dest EEW encoded in the instruction and EMUL=(EEW/SEW)*LMUL
case RISCV::VLM_V:
case RISCV::VSM_V:
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@topperc topperc Jan 8, 2025

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No tests for VSM?

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@michaelmaitland michaelmaitland Jan 8, 2025

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Added, although I'm not sure that it makes sense to have an incompatible_eew test does it?

return OperandInfo(RISCVVType::getEMULEqualsEEWDivSEWTimesLMUL(0, MI), 0);
case RISCV::VLE8_V:
case RISCV::VSE8_V:
case RISCV::VLSE8_V:
Expand Down Expand Up @@ -742,6 +745,7 @@ static bool isSupportedInstr(const MachineInstr &MI) {
switch (RVV->BaseInstr) {
// Vector Unit-Stride Instructions
// Vector Strided Instructions
case RISCV::VLM_V:
case RISCV::VLE8_V:
case RISCV::VLSE8_V:
case RISCV::VLE16_V:
Expand Down
50 changes: 50 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
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Expand Up @@ -573,6 +573,26 @@ body: |
PseudoVSE8_V_MF2 %x, $noreg, 1, 3 /* e8 */
...
---
name: vsm_v
body: |
bb.0:
; CHECK-LABEL: name: vsm_v
; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */
; CHECK-NEXT: PseudoVSM_V_B8 %x, $noreg, 1, 0 /* e8 */
%x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0
PseudoVSM_V_B8 %x, $noreg, 1, 0
...
---
name: vsm_v_incompatible_emul
body: |
bb.0:
; CHECK-LABEL: name: vsm_v_incompatible_emul
; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */
; CHECK-NEXT: PseudoVSM_V_B16 %x, $noreg, 1, 0 /* e8 */
%x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0
PseudoVSM_V_B16 %x, $noreg, 1, 0
...
---
name: vleN_v
body: |
bb.0:
Expand Down Expand Up @@ -603,6 +623,36 @@ body: |
%x:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 3 /* e8 */, 0
...
---
name: vlm_v
body: |
bb.0:
; CHECK-LABEL: name: vlm_v
; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, 1, 0 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0 /* e8 */
%x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0
%y:vr = PseudoVMAND_MM_B8 $noreg, %x, 1, 0
...
---
name: vlm_v_incompatible_eew
body: |
bb.0:
; CHECK-LABEL: name: vlm_v_incompatible_eew
; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0 /* tu, mu */
%x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0
%y:vr = PseudoVADD_VV_M1 $noreg, $noreg, %x, 1, 4 /* e16 */, 0
...
---
name: vlm_v_incompatible_emul
body: |
bb.0:
; CHECK-LABEL: name: vlm_v_incompatible_emul
; CHECK: %x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 /* e8 */
%x:vr = PseudoVLM_V_B8 $noreg, $noreg, -1, 0, 0
%y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0
...
---
name: vsseN_v
body: |
bb.0:
Expand Down
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