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[AMDGPU] Update PromoteAlloca to handle GEPs with variable offset. #122342

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Merged
merged 6 commits into from
Feb 24, 2025
Merged

[AMDGPU] Update PromoteAlloca to handle GEPs with variable offset. #122342

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1093642
[AMDGPU] Update PromoteAlloca to handle GEPs with variable offset.
sgundapa Jan 9, 2025
9b7403a
[AMDGPU] Update PromoteAlloca to handle updated GEP Indexes.
sgundapa Jan 30, 2025
d443b33
Merge branch 'llvm:main' into pro_alloc_crash
sgundapa Feb 10, 2025
13a43bd
[AMDGPU] Update PromoteAlloca to handle changed GEP Indexes.
sgundapa Feb 10, 2025
bf8a22d
Update llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
sgundapa Feb 24, 2025
3e8e15f
clang-format fix
arsenm Feb 24, 2025
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66 changes: 45 additions & 21 deletions llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -385,28 +385,20 @@ static bool isSupportedMemset(MemSetInst *I, AllocaInst *AI,
match(I->getOperand(2), m_SpecificInt(Size)) && !I->isVolatile();
}

static Value *
calculateVectorIndex(Value *Ptr,
const std::map<GetElementPtrInst *, Value *> &GEPIdx) {
auto *GEP = dyn_cast<GetElementPtrInst>(Ptr->stripPointerCasts());
if (!GEP)
return ConstantInt::getNullValue(Type::getInt32Ty(Ptr->getContext()));

auto I = GEPIdx.find(GEP);
assert(I != GEPIdx.end() && "Must have entry for GEP!");
return I->second;
}

static Value *GEPToVectorIndex(GetElementPtrInst *GEP, AllocaInst *Alloca,
Type *VecElemTy, const DataLayout &DL) {
static Value *GEPToVectorIndex(GetElementPtrInst *GEP, Type *VecElemTy,
const DataLayout &DL,
AllocaInst *Alloca = nullptr) {
// TODO: Extracting a "multiple of X" from a GEP might be a useful generic
// helper.
unsigned BW = DL.getIndexTypeSizeInBits(GEP->getType());
SmallMapVector<Value *, APInt, 4> VarOffsets;
APInt ConstOffset(BW, 0);
if (GEP->getPointerOperand()->stripPointerCasts() != Alloca ||
!GEP->collectOffset(DL, BW, VarOffsets, ConstOffset))
return nullptr;

bool CanCollect = GEP->collectOffset(DL, BW, VarOffsets, ConstOffset);

if (Alloca)
if (GEP->getPointerOperand()->stripPointerCasts() != Alloca || !CanCollect)
return nullptr;

unsigned VecElemSize = DL.getTypeAllocSize(VecElemTy);
if (VarOffsets.size() > 1)
Expand All @@ -430,6 +422,36 @@ static Value *GEPToVectorIndex(GetElementPtrInst *GEP, AllocaInst *Alloca,
return ConstantInt::get(GEP->getContext(), Quot);
}

// Function to check if a Value is an operand of a GetElementPtrInst.
static bool isValueInGEP(GetElementPtrInst *GEP, Value *ValueToCheck) {
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@arsenm arsenm Jan 31, 2025

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This still feels like too specific of a check, and the same form of pattern could arise from other instructions. It would be better to detect it as part of the transformation

if (!GEP || !ValueToCheck)
return false;

for (unsigned i = 0; i < GEP->getNumOperands(); ++i)
if (GEP->getOperand(i) == ValueToCheck)
return true;

return false;
}

static Value *
calculateVectorIndex(Value *Ptr, std::map<GetElementPtrInst *, Value *> &GEPIdx,
Type *VecElemTy, const DataLayout &DL) {
auto *GEP = dyn_cast<GetElementPtrInst>(Ptr->stripPointerCasts());
if (!GEP)
return ConstantInt::getNullValue(Type::getInt32Ty(Ptr->getContext()));

// Update the cached index if the value is changed.
if (!isValueInGEP(GEP, GEPIdx[GEP])) {
Value *Index = GEPToVectorIndex(GEP, VecElemTy, DL);
GEPIdx[GEP] = Index;
}

auto I = GEPIdx.find(GEP);
assert(I != GEPIdx.end() && "Must have entry for GEP!");
return I->second;
}

/// Promotes a single user of the alloca to a vector form.
///
/// \param Inst Instruction to be promoted.
Expand Down Expand Up @@ -496,7 +518,7 @@ static Value *promoteAllocaUserToVector(
}

Value *Index = calculateVectorIndex(
cast<LoadInst>(Inst)->getPointerOperand(), GEPVectorIdx);
cast<LoadInst>(Inst)->getPointerOperand(), GEPVectorIdx, VecEltTy, DL);

// We're loading the full vector.
Type *AccessTy = Inst->getType();
Expand Down Expand Up @@ -552,7 +574,8 @@ static Value *promoteAllocaUserToVector(
// to know the current value. If this is a store of a single element, we
// need to know the value.
StoreInst *SI = cast<StoreInst>(Inst);
Value *Index = calculateVectorIndex(SI->getPointerOperand(), GEPVectorIdx);
Value *Index = calculateVectorIndex(SI->getPointerOperand(), GEPVectorIdx,
VecEltTy, DL);
Value *Val = SI->getValueOperand();

// We're storing the full vector, we can handle this without knowing CurVal.
Expand Down Expand Up @@ -815,7 +838,7 @@ bool AMDGPUPromoteAllocaImpl::tryPromoteAllocaToVector(AllocaInst &Alloca) {
if (auto *GEP = dyn_cast<GetElementPtrInst>(Inst)) {
// If we can't compute a vector index from this GEP, then we can't
// promote this alloca to vector.
Value *Index = GEPToVectorIndex(GEP, &Alloca, VecEltTy, *DL);
Value *Index = GEPToVectorIndex(GEP, VecEltTy, *DL, &Alloca);
if (!Index)
return RejectUser(Inst, "cannot compute vector index for GEP");

Expand Down Expand Up @@ -850,7 +873,8 @@ bool AMDGPUPromoteAllocaImpl::tryPromoteAllocaToVector(AllocaInst &Alloca) {
if (Ptr != &Alloca && !GEPVectorIdx.count(GEP))
return nullptr;

return dyn_cast<ConstantInt>(calculateVectorIndex(Ptr, GEPVectorIdx));
return dyn_cast<ConstantInt>(
calculateVectorIndex(Ptr, GEPVectorIdx, VecEltTy, *DL));
};

unsigned OpNum = U->getOperandNo();
Expand Down
28 changes: 28 additions & 0 deletions llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -122,6 +122,34 @@ define amdgpu_vs void @promote_load_from_store_aggr() #0 {
ret void
}

%Block4 = type { [2 x i32], i32 }
@block4 = external addrspace(1) global %Block4
%gl_PV = type { <4 x i32>, i32, [1 x i32], [1 x i32] }
@pv1 = external addrspace(1) global %gl_PV

; This should not crash on an aliased variable offset that can be
; optimized out (variable %aliasToG1 in the test)
define amdgpu_vs void @promote_load_from_store_aggr_varoff(<4 x i32> %input) {
; CHECK-LABEL: @promote_load_from_store_aggr_varoff(
; CHECK-NEXT: [[FOO3_UNPACK2:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @block4, i64 8), align 4
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i32> undef, i32 [[FOO3_UNPACK2]], i32 2
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <3 x i32> [[TMP1]], i32 [[FOO3_UNPACK2]]
; CHECK-NEXT: [[FOO12:%.*]] = insertelement <4 x i32> %input, i32 [[TMP2]], i64 3
; CHECK-NEXT: store <4 x i32> [[FOO12]], ptr addrspace(1) @pv1, align 16
; CHECK-NEXT: ret void
;
%f1 = alloca [3 x i32], align 4, addrspace(5)
%G1 = getelementptr inbounds i8, ptr addrspace(5) %f1, i32 8
%foo3.unpack2 = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @block4, i64 8), align 4
store i32 %foo3.unpack2, ptr addrspace(5) %G1, align 4
%aliasToG1 = load i32, ptr addrspace(5) %G1, align 4
%foo5 = getelementptr [3 x i32], ptr addrspace(5) %f1, i32 0, i32 %aliasToG1
%foo6 = load i32, ptr addrspace(5) %foo5, align 4
%foo12 = insertelement <4 x i32> %input, i32 %foo6, i64 3
store <4 x i32> %foo12, ptr addrspace(1) @pv1, align 16
ret void
}

define amdgpu_vs void @promote_memmove_aggr() #0 {
; CHECK-LABEL: @promote_memmove_aggr(
; CHECK-NEXT: store float 1.000000e+00, ptr addrspace(1) @pv, align 4
Expand Down
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