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Revert "[ADT] Fix specialization of ValueIsPresent for PointerUnion" #122557

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Merged
merged 1 commit into from
Jan 11, 2025
Merged

Revert "[ADT] Fix specialization of ValueIsPresent for PointerUnion" #122557

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8 changes: 4 additions & 4 deletions llvm/include/llvm/Support/Casting.h
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Original file line number Diff line number Diff line change
Expand Up @@ -614,12 +614,12 @@ template <typename T> struct ValueIsPresent<std::optional<T>> {
static inline decltype(auto) unwrapValue(std::optional<T> &t) { return *t; }
};

// If something is "nullable" then we just cast it to bool to see if it exists.
// If something is "nullable" then we just compare it to nullptr to see if it
// exists.
template <typename T>
struct ValueIsPresent<
T, std::enable_if_t<IsNullable<T> && std::is_constructible_v<bool, T>>> {
struct ValueIsPresent<T, std::enable_if_t<IsNullable<T>>> {
using UnwrappedType = T;
static inline bool isPresent(const T &t) { return static_cast<bool>(t); }
static inline bool isPresent(const T &t) { return t != T(nullptr); }
static inline decltype(auto) unwrapValue(T &t) { return t; }
};

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4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/RegisterBankInfo.cpp
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Expand Up @@ -134,10 +134,10 @@ const TargetRegisterClass *RegisterBankInfo::constrainGenericRegister(

// If the register already has a class, fallback to MRI::constrainRegClass.
auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
if (isa_and_present<const TargetRegisterClass *>(RegClassOrBank))
if (isa<const TargetRegisterClass *>(RegClassOrBank))
return MRI.constrainRegClass(Reg, &RC);

const auto *RB = dyn_cast_if_present<const RegisterBank *>(RegClassOrBank);
const RegisterBank *RB = cast<const RegisterBank *>(RegClassOrBank);
// Otherwise, all we can do is ensure the bank covers the class, and set it.
if (RB && !RB->covers(RC))
return nullptr;
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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Expand Up @@ -3708,10 +3708,10 @@ const TargetRegisterClass *
SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
const MachineRegisterInfo &MRI) const {
const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());
if (const auto *RB = dyn_cast_if_present<const RegisterBank *>(RCOrRB))
if (const RegisterBank *RB = dyn_cast<const RegisterBank *>(RCOrRB))
return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB);

if (const auto *RC = dyn_cast_if_present<const TargetRegisterClass *>(RCOrRB))
if (const auto *RC = dyn_cast<const TargetRegisterClass *>(RCOrRB))
return getAllocatableClass(RC);

return nullptr;
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5 changes: 0 additions & 5 deletions llvm/unittests/ADT/PointerUnionTest.cpp
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Expand Up @@ -208,11 +208,6 @@ TEST_F(PointerUnionTest, NewCastInfra) {
EXPECT_FALSE(isa<float *>(d4null));
EXPECT_FALSE(isa<long long *>(d4null));

EXPECT_FALSE(isa_and_present<int *>(i4null));
EXPECT_FALSE(isa_and_present<float *>(f4null));
EXPECT_FALSE(isa_and_present<long long *>(l4null));
EXPECT_FALSE(isa_and_present<double *>(d4null));

// test cast<>
EXPECT_EQ(cast<float *>(a), &f);
EXPECT_EQ(cast<int *>(b), &i);
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