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[RISCV][VLOPT] Handle tied pseudos in getOperandInfo #123170

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Merged
lukel97 merged 3 commits into from
Jan 16, 2025
Merged

[RISCV][VLOPT] Handle tied pseudos in getOperandInfo #123170

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e0f300b
Precommit tests
lukel97 Jan 16, 2025
a0f253a
[RISCV][VLOPT] Handle tied pseudos in getOperandInfo
lukel97 Jan 16, 2025
5ba40f6
Fix test name
lukel97 Jan 16, 2025
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5 changes: 4 additions & 1 deletion llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -206,6 +206,7 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm();

const bool HasPassthru = RISCVII::isFirstDefTiedToFirstUse(MI.getDesc());
const bool IsTied = RISCVII::isTiedPseudo(MI.getDesc().TSFlags);

// We bail out early for instructions that have passthru with non NoRegister,
// which means they are using TU policy. We are not interested in these
Expand Down Expand Up @@ -568,7 +569,8 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
case RISCV::VFWADD_WV:
case RISCV::VFWSUB_WF:
case RISCV::VFWSUB_WV: {
bool IsOp1 = HasPassthru ? MO.getOperandNo() == 2 : MO.getOperandNo() == 1;
bool IsOp1 = (HasPassthru && !IsTied) ? MO.getOperandNo() == 2
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@wangpc-pp wangpc-pp Jan 16, 2025

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I am inclined to use another name instead of IsOp1 because it doesn't make sense here, IsVS1 seems to be more suitable.
Since there are more other cases, this can be a NFC follow-up. :-)

: MO.getOperandNo() == 1;
bool TwoTimes = IsMODef || IsOp1;
return TwoTimes ? MILog2SEW + 1 : MILog2SEW;
}
Expand Down Expand Up @@ -610,6 +612,7 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
case RISCV::VFNCVT_F_F_W:
case RISCV::VFNCVT_ROD_F_F_W:
case RISCV::VFNCVTBF16_F_F_W: {
assert(!IsTied);
bool IsOp1 = HasPassthru ? MO.getOperandNo() == 2 : MO.getOperandNo() == 1;
bool TwoTimes = IsOp1;
return TwoTimes ? MILog2SEW + 1 : MILog2SEW;
Expand Down
30 changes: 30 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
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Expand Up @@ -243,6 +243,36 @@ body: |
%y:vrm2 = PseudoVWADD_WV_M1 $noreg, $noreg, %x, 1, 3 /* e8 */, 0
...
---
name: tied_vwop_wv_vs1
body: |
bb.0:
; CHECK-LABEL: name: tied_vwop_wv_vs1
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
%y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0
...
---
name: tied_vwop_wv_vs1_incompatible_eew
body: |
bb.0:
; CHECK-LABEL: name: tied_vwop_wv_vs1_incompatible_eew
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
%y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0
...
---
name: tied_vwop_wv_vs1_incompatible_emul
body: |
bb.0:
; CHECK-LABEL: name: tied_vwop_wv_vs1_incompatible_emul
; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
%x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
%y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0
...
---
name: vop_vf2_vd
body: |
bb.0:
Expand Down
10 changes: 9 additions & 1 deletion llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
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Expand Up @@ -140,4 +140,12 @@ body: |
%x:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, $noreg, 7, -1, 4 /* e16 */, 0 /* tu, mu */, implicit $frm
%y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0
...

---
name: vwaddu_
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@michaelmaitland michaelmaitland Jan 16, 2025

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trailing _?

body: |
bb.0:
; CHECK-LABEL: name: vwaddu_
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: early-clobber %y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
%y:vrm2 = PseudoVWADD_WV_M1_TIED $noreg, %x, 1, 3 /* e8 */, 0 /* tu, mu */
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