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[compiler-rt] Make Arm builtins aware of endianness in VMOVs #123204

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Merged
merged 5 commits into from
Jan 22, 2025
Merged

[compiler-rt] Make Arm builtins aware of endianness in VMOVs #123204

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b60c65d
[compiler-rt] Make __aeabi_dcmp aware of endianness
vhscampos Jan 16, 2025
dd31999
Extend patch to all arm builtins that have the same pattern
vhscampos Jan 20, 2025
862fdf7
Fix clang-format error
vhscampos Jan 20, 2025
02ff3e3
Fix typo in macro defined by endianness
vhscampos Jan 20, 2025
424219d
Fix typo in register name: r7 to d7
vhscampos Jan 20, 2025
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6 changes: 3 additions & 3 deletions compiler-rt/lib/builtins/arm/adddf3vfp.S
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Expand Up @@ -19,10 +19,10 @@ DEFINE_COMPILERRT_FUNCTION(__adddf3vfp)
#if defined(COMPILER_RT_ARMHF_TARGET)
vadd.f64 d0, d0, d1
#else
vmov d6, r0, r1 // move first param from r0/r1 pair into d6
vmov d7, r2, r3 // move second param from r2/r3 pair into d7
VMOV_TO_DOUBLE(d6, r0, r1) // move first param from r0/r1 pair into d6
VMOV_TO_DOUBLE(d7, r2, r3) // move second param from r2/r3 pair into d7
vadd.f64 d6, d6, d7
vmov r0, r1, d6 // move result back to r0/r1 pair
VMOV_FROM_DOUBLE(r0, r1, d6) // move result back to r0/r1 pair
#endif
bx lr
END_COMPILERRT_FUNCTION(__adddf3vfp)
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6 changes: 3 additions & 3 deletions compiler-rt/lib/builtins/arm/aeabi_dcmp.S
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Expand Up @@ -18,9 +18,9 @@
// }

#if defined(COMPILER_RT_ARMHF_TARGET)
# define CONVERT_DCMP_ARGS_TO_DF2_ARGS \
vmov d0, r0, r1 SEPARATOR \
vmov d1, r2, r3
# define CONVERT_DCMP_ARGS_TO_DF2_ARGS \
VMOV_TO_DOUBLE(d0, r0, r1) \
VMOV_TO_DOUBLE(d1, r2, r3)
#else
# define CONVERT_DCMP_ARGS_TO_DF2_ARGS
#endif
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6 changes: 3 additions & 3 deletions compiler-rt/lib/builtins/arm/divdf3vfp.S
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Expand Up @@ -20,10 +20,10 @@ DEFINE_COMPILERRT_FUNCTION(__divdf3vfp)
#if defined(COMPILER_RT_ARMHF_TARGET)
vdiv.f64 d0, d0, d1
#else
vmov d6, r0, r1 // move first param from r0/r1 pair into d6
vmov d7, r2, r3 // move second param from r2/r3 pair into d7
VMOV_TO_DOUBLE(d6, r0, r1) // move first param from r0/r1 pair into d6
VMOV_TO_DOUBLE(d7, r2, r3) // move second param from r2/r3 pair into d7
vdiv.f64 d5, d6, d7
vmov r0, r1, d5 // move result back to r0/r1 pair
VMOV_FROM_DOUBLE(r0, r1, d5) // move result back to r0/r1 pair
#endif
bx lr
END_COMPILERRT_FUNCTION(__divdf3vfp)
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4 changes: 2 additions & 2 deletions compiler-rt/lib/builtins/arm/eqdf2vfp.S
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Expand Up @@ -20,8 +20,8 @@ DEFINE_COMPILERRT_FUNCTION(__eqdf2vfp)
#if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f64 d0, d1
#else
vmov d6, r0, r1 // load r0/r1 pair in double register
vmov d7, r2, r3 // load r2/r3 pair in double register
VMOV_TO_DOUBLE(d6, r0, r1) // load r0/r1 pair in double register
VMOV_TO_DOUBLE(d7, r2, r3) // load r2/r3 pair in double register
vcmp.f64 d6, d7
#endif
vmrs apsr_nzcv, fpscr
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2 changes: 1 addition & 1 deletion compiler-rt/lib/builtins/arm/extendsfdf2vfp.S
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Expand Up @@ -23,7 +23,7 @@ DEFINE_COMPILERRT_FUNCTION(__extendsfdf2vfp)
#else
vmov s15, r0 // load float register from R0
vcvt.f64.f32 d7, s15 // convert single to double
vmov r0, r1, d7 // return result in r0/r1 pair
VMOV_FROM_DOUBLE(r0, r1, d7) // return result in r0/r1 pair
#endif
bx lr
END_COMPILERRT_FUNCTION(__extendsfdf2vfp)
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2 changes: 1 addition & 1 deletion compiler-rt/lib/builtins/arm/fixdfsivfp.S
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Expand Up @@ -22,7 +22,7 @@ DEFINE_COMPILERRT_FUNCTION(__fixdfsivfp)
vcvt.s32.f64 s0, d0
vmov r0, s0
#else
vmov d7, r0, r1 // load double register from R0/R1
VMOV_TO_DOUBLE(d7, r0, r1) // load double register from R0/R1
vcvt.s32.f64 s15, d7 // convert double to 32-bit int into s15
vmov r0, s15 // move s15 to result register
#endif
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2 changes: 1 addition & 1 deletion compiler-rt/lib/builtins/arm/fixunsdfsivfp.S
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Expand Up @@ -23,7 +23,7 @@ DEFINE_COMPILERRT_FUNCTION(__fixunsdfsivfp)
vcvt.u32.f64 s0, d0
vmov r0, s0
#else
vmov d7, r0, r1 // load double register from R0/R1
VMOV_TO_DOUBLE(d7, r0, r1) // load double register from R0/R1
vcvt.u32.f64 s15, d7 // convert double to 32-bit int into s15
vmov r0, s15 // move s15 to result register
#endif
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2 changes: 1 addition & 1 deletion compiler-rt/lib/builtins/arm/floatsidfvfp.S
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Expand Up @@ -24,7 +24,7 @@ DEFINE_COMPILERRT_FUNCTION(__floatsidfvfp)
#else
vmov s15, r0 // move int to float register s15
vcvt.f64.s32 d7, s15 // convert 32-bit int in s15 to double in d7
vmov r0, r1, d7 // move d7 to result register pair r0/r1
VMOV_FROM_DOUBLE(r0, r1, d7) // move d7 to result register pair r0/r1
#endif
bx lr
END_COMPILERRT_FUNCTION(__floatsidfvfp)
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2 changes: 1 addition & 1 deletion compiler-rt/lib/builtins/arm/floatunssidfvfp.S
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Expand Up @@ -24,7 +24,7 @@ DEFINE_COMPILERRT_FUNCTION(__floatunssidfvfp)
#else
vmov s15, r0 // move int to float register s15
vcvt.f64.u32 d7, s15 // convert 32-bit int in s15 to double in d7
vmov r0, r1, d7 // move d7 to result register pair r0/r1
VMOV_FROM_DOUBLE(r0, r1, r7) // move d7 to result register pair r0/r1
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@smithp35 smithp35 Jan 20, 2025

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Did you mean vmov r0, r1, d7 here?

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@vhscampos vhscampos Jan 20, 2025

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Thanks. Fixed.

The typo didn't cause any failures in the picolibc tests. One indication that these parts here are undertested.

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@smithp35 smithp35 Jan 20, 2025

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It looks like the compiler-rt test suite would have caught this if it were built and run on exactly the right target with test/floatunssidfvfp_test.c

It looks like the little-endian side should be tested via the clang-armv7-2stage https://lab.llvm.org/buildbot/#/builders/79 as that will run the compiler-rt unit tests directly.

Testing big-endian is more difficult as we'd likely need to find a very old linux big-endian eabihf sysroot and use qemu-arm as our test executor.

#endif
bx lr
END_COMPILERRT_FUNCTION(__floatunssidfvfp)
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4 changes: 2 additions & 2 deletions compiler-rt/lib/builtins/arm/gedf2vfp.S
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Expand Up @@ -21,8 +21,8 @@ DEFINE_COMPILERRT_FUNCTION(__gedf2vfp)
#if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f64 d0, d1
#else
vmov d6, r0, r1 // load r0/r1 pair in double register
vmov d7, r2, r3 // load r2/r3 pair in double register
VMOV_TO_DOUBLE(d6, r0, r1) // load r0/r1 pair in double register
VMOV_TO_DOUBLE(d7, r2, r3) // load r2/r3 pair in double register
vcmp.f64 d6, d7
#endif
vmrs apsr_nzcv, fpscr
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4 changes: 2 additions & 2 deletions compiler-rt/lib/builtins/arm/gtdf2vfp.S
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Expand Up @@ -21,8 +21,8 @@ DEFINE_COMPILERRT_FUNCTION(__gtdf2vfp)
#if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f64 d0, d1
#else
vmov d6, r0, r1 // load r0/r1 pair in double register
vmov d7, r2, r3 // load r2/r3 pair in double register
VMOV_TO_DOUBLE(d6, r0, r1) // load r0/r1 pair in double register
VMOV_TO_DOUBLE(d7, r2, r3) // load r2/r3 pair in double register
vcmp.f64 d6, d7
#endif
vmrs apsr_nzcv, fpscr
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4 changes: 2 additions & 2 deletions compiler-rt/lib/builtins/arm/ledf2vfp.S
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Expand Up @@ -21,8 +21,8 @@ DEFINE_COMPILERRT_FUNCTION(__ledf2vfp)
#if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f64 d0, d1
#else
vmov d6, r0, r1 // load r0/r1 pair in double register
vmov d7, r2, r3 // load r2/r3 pair in double register
VMOV_TO_DOUBLE(d6, r0, r1) // load r0/r1 pair in double register
VMOV_TO_DOUBLE(d7, r2, r3) // load r2/r3 pair in double register
vcmp.f64 d6, d7
#endif
vmrs apsr_nzcv, fpscr
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4 changes: 2 additions & 2 deletions compiler-rt/lib/builtins/arm/ltdf2vfp.S
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Expand Up @@ -21,8 +21,8 @@ DEFINE_COMPILERRT_FUNCTION(__ltdf2vfp)
#if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f64 d0, d1
#else
vmov d6, r0, r1 // load r0/r1 pair in double register
vmov d7, r2, r3 // load r2/r3 pair in double register
VMOV_TO_DOUBLE(d6, r0, r1) // load r0/r1 pair in double register
VMOV_TO_DOUBLE(d7, r2, r3) // load r2/r3 pair in double register
vcmp.f64 d6, d7
#endif
vmrs apsr_nzcv, fpscr
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6 changes: 3 additions & 3 deletions compiler-rt/lib/builtins/arm/muldf3vfp.S
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Expand Up @@ -20,10 +20,10 @@ DEFINE_COMPILERRT_FUNCTION(__muldf3vfp)
#if defined(COMPILER_RT_ARMHF_TARGET)
vmul.f64 d0, d0, d1
#else
vmov d6, r0, r1 // move first param from r0/r1 pair into d6
vmov d7, r2, r3 // move second param from r2/r3 pair into d7
VMOV_TO_DOUBLE(d6, r0, r1) // move first param from r0/r1 pair into d6
VMOV_TO_DOUBLE(d7, r2, r3) // move second param from r2/r3 pair into d7
vmul.f64 d6, d6, d7
vmov r0, r1, d6 // move result back to r0/r1 pair
VMOV_FROM_DOUBLE(r0, r1, d6) // move result back to r0/r1 pair
#endif
bx lr
END_COMPILERRT_FUNCTION(__muldf3vfp)
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4 changes: 2 additions & 2 deletions compiler-rt/lib/builtins/arm/nedf2vfp.S
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Expand Up @@ -20,8 +20,8 @@ DEFINE_COMPILERRT_FUNCTION(__nedf2vfp)
#if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f64 d0, d1
#else
vmov d6, r0, r1 // load r0/r1 pair in double register
vmov d7, r2, r3 // load r2/r3 pair in double register
VMOV_TO_DOUBLE(d6, r0, r1) // load r0/r1 pair in double register
VMOV_TO_DOUBLE(d7, r2, r3) // load r2/r3 pair in double register
vcmp.f64 d6, d7
#endif
vmrs apsr_nzcv, fpscr
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6 changes: 3 additions & 3 deletions compiler-rt/lib/builtins/arm/subdf3vfp.S
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Expand Up @@ -20,10 +20,10 @@ DEFINE_COMPILERRT_FUNCTION(__subdf3vfp)
#if defined(COMPILER_RT_ARMHF_TARGET)
vsub.f64 d0, d0, d1
#else
vmov d6, r0, r1 // move first param from r0/r1 pair into d6
vmov d7, r2, r3 // move second param from r2/r3 pair into d7
VMOV_TO_DOUBLE(d6, r0, r1) // move first param from r0/r1 pair into d6
VMOV_TO_DOUBLE(d7, r2, r3) // move second param from r2/r3 pair into d7
vsub.f64 d6, d6, d7
vmov r0, r1, d6 // move result back to r0/r1 pair
VMOV_FROM_DOUBLE(r0, r1, d6) // move result back to r0/r1 pair
#endif
bx lr
END_COMPILERRT_FUNCTION(__subdf3vfp)
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2 changes: 1 addition & 1 deletion compiler-rt/lib/builtins/arm/truncdfsf2vfp.S
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Expand Up @@ -21,7 +21,7 @@ DEFINE_COMPILERRT_FUNCTION(__truncdfsf2vfp)
#if defined(COMPILER_RT_ARMHF_TARGET)
vcvt.f32.f64 s0, d0
#else
vmov d7, r0, r1 // load double from r0/r1 pair
VMOV_TO_DOUBLE(d7, r0, r1) // load double from r0/r1 pair
vcvt.f32.f64 s15, d7 // convert double to single (trucate precision)
vmov r0, s15 // return result in r0
#endif
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4 changes: 2 additions & 2 deletions compiler-rt/lib/builtins/arm/unorddf2vfp.S
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Expand Up @@ -21,8 +21,8 @@ DEFINE_COMPILERRT_FUNCTION(__unorddf2vfp)
#if defined(COMPILER_RT_ARMHF_TARGET)
vcmp.f64 d0, d1
#else
vmov d6, r0, r1 // load r0/r1 pair in double register
vmov d7, r2, r3 // load r2/r3 pair in double register
VMOV_TO_DOUBLE(d6, r0, r1) // load r0/r1 pair in double register
VMOV_TO_DOUBLE(d7, r2, r3) // load r2/r3 pair in double register
vcmp.f64 d6, d7
#endif
vmrs apsr_nzcv, fpscr
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12 changes: 12 additions & 0 deletions compiler-rt/lib/builtins/assembly.h
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Expand Up @@ -290,4 +290,16 @@
CFI_END
#endif

#ifdef __arm__
#include "int_endianness.h"

#if __YUGA_BIG_ENDIAN
#define VMOV_TO_DOUBLE(dst, src0, src1) vmov dst, src1, src0 SEPARATOR
#define VMOV_FROM_DOUBLE(dst0, dst1, src) vmov dst1, dst0, src SEPARATOR
#else
#define VMOV_TO_DOUBLE(dst, src0, src1) vmov dst, src0, src1 SEPARATOR
#define VMOV_FROM_DOUBLE(dst0, dst1, src) vmov dst0, dst1, src SEPARATOR
#endif
#endif

#endif // COMPILERRT_ASSEMBLY_H
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