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[AArch64] FEAT_SPEv1p2 is optional in v8.7-A and v9.2-A #123336

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Merged
merged 5 commits into from
Jan 21, 2025
Merged

[AArch64] FEAT_SPEv1p2 is optional in v8.7-A and v9.2-A #123336

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8f958b7
[AArch64] refactor optional v9.x features inherited from v8.(x+5) (NFC)
ostannard Jan 17, 2025
cb08d6c
[AArch64] FEAT_SPEv1p2 is optional in v8.7-A and v9.2-A
ostannard Jan 17, 2025
eef8255
Remove FEAT_SPE* from Ampere1B
ostannard Jan 17, 2025
3a3de8f
Fix Ampere1B test
ostannard Jan 17, 2025
faad4b3
Remove FEAT_SPE* from Fujitsu Monaka
ostannard Jan 20, 2025
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2 changes: 1 addition & 1 deletion clang/test/CodeGen/AArch64/targetattr.c
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Expand Up @@ -218,7 +218,7 @@ void applem4() {}
// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "branch-target-enforcement" "guarded-control-stack" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-v9.3a" }
// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m4" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fpac,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+sme,+sme-f64f64,+sme-i16i64,+sme2,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8a,+wfxt" }
// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m4" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fpac,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+sme,+sme-f64f64,+sme-i16i64,+sme2,+spe-eef,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8.7a,+v8a,+wfxt" }
//.
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
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1 change: 0 additions & 1 deletion clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c
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Expand Up @@ -46,7 +46,6 @@
// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
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1 change: 0 additions & 1 deletion clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c
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Expand Up @@ -46,7 +46,6 @@
// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
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16 changes: 9 additions & 7 deletions llvm/lib/Target/AArch64/AArch64Features.td
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Expand Up @@ -859,8 +859,8 @@ def HasV8_6aOps : Architecture64<8, 6, "a", "v8.6a",
FeatureEnhancedCounterVirtualization, FeatureMatMulInt8],
!listconcat(HasV8_5aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8])>;
def HasV8_7aOps : Architecture64<8, 7, "a", "v8.7a",
[HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX, FeatureSPE_EEF],
!listconcat(HasV8_6aOps.DefaultExts, [FeatureWFxT])>;
[HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX],
!listconcat(HasV8_6aOps.DefaultExts, [FeatureWFxT, FeatureSPE_EEF])>;
def HasV8_8aOps : Architecture64<8, 8, "a", "v8.8a",
[HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI],
!listconcat(HasV8_7aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>;
Expand All @@ -875,17 +875,19 @@ def HasV9_0aOps : Architecture64<9, 0, "a", "v9a",
FeatureSVE2])>;
def HasV9_1aOps : Architecture64<9, 1, "a", "v9.1a",
[HasV8_6aOps, HasV9_0aOps],
!listconcat(HasV9_0aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8, FeatureRME])>;
!listconcat(HasV9_0aOps.DefaultExts, HasV8_6aOps.DefaultExts,
[FeatureRME])>;
def HasV9_2aOps : Architecture64<9, 2, "a", "v9.2a",
[HasV8_7aOps, HasV9_1aOps],
!listconcat(HasV9_1aOps.DefaultExts, [FeatureMEC, FeatureWFxT])>;
!listconcat(HasV9_1aOps.DefaultExts, HasV8_7aOps.DefaultExts,
[FeatureMEC])>;
def HasV9_3aOps : Architecture64<9, 3, "a", "v9.3a",
[HasV8_8aOps, HasV9_2aOps],
!listconcat(HasV9_2aOps.DefaultExts, [FeatureMOPS, FeatureHBC])>;
!listconcat(HasV9_2aOps.DefaultExts, HasV8_8aOps.DefaultExts, [])>;
def HasV9_4aOps : Architecture64<9, 4, "a", "v9.4a",
[HasV8_9aOps, HasV9_3aOps],
!listconcat(HasV9_3aOps.DefaultExts, [FeatureSPECRES2, FeatureCSSC,
FeatureRASv2, FeatureSVE2p1])>;
!listconcat(HasV9_3aOps.DefaultExts, HasV8_9aOps.DefaultExts,
[FeatureSVE2p1])>;
def HasV9_5aOps : Architecture64<9, 5, "a", "v9.5a",
[HasV9_4aOps, FeatureCPA],
!listconcat(HasV9_4aOps.DefaultExts, [FeatureCPA, FeatureLUT, FeatureFAMINMAX])>;
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7 changes: 4 additions & 3 deletions llvm/lib/Target/AArch64/AArch64Processors.td
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Expand Up @@ -856,7 +856,7 @@ def ProcessorFeatures {
FeatureSSBS, FeatureLS64, FeatureCLRBHB,
FeatureSPECRES2, FeatureSVEAES, FeatureSVE2SM4,
FeatureSVE2SHA3, FeatureSVE2, FeatureSVEBitPerm, FeatureETE,
FeatureMEC, FeatureFP8DOT2];
FeatureMEC, FeatureFP8DOT2, FeatureSPE_EEF];
list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureSHA2, FeatureAES,
FeatureFullFP16, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM,
FeatureFPARMv8];
Expand Down Expand Up @@ -923,7 +923,8 @@ def ProcessorFeatures {
FeatureComplxNum, FeatureCRC, FeatureJS,
FeatureLSE, FeaturePAuth, FeatureFPAC,
FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureDotProd, FeatureMatMulInt8];
FeatureDotProd, FeatureMatMulInt8,
FeatureSPE_EEF];
list<SubtargetFeature> ExynosM3 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES,
FeaturePerfMon, FeatureNEON, FeatureFPARMv8];
list<SubtargetFeature> ExynosM4 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureDotProd,
Expand Down Expand Up @@ -1046,7 +1047,7 @@ def ProcessorFeatures {
FeatureCRC, FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8,
FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS, FeatureRCPC,
FeatureCCIDX,
FeatureRDM];
FeatureRDM, FeatureSPE_EEF];

list<SubtargetFeature> Oryon = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
FeatureRandGen,
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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/spe.s
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@@ -1,5 +1,5 @@
// RUN: llvm-mc -triple aarch64 -mattr +spe-eef -show-encoding %s 2>%t | FileCheck %s
// RUN: llvm-mc -triple aarch64 -mattr +v8.7a -show-encoding %s 2>%t | FileCheck %s
// RUN: not llvm-mc -triple aarch64 -mattr +v8.7a %s 2>&1 | FileCheck --check-prefix=CHECK-NO-SPE-EEF-ERR %s
// RUN: not llvm-mc -triple aarch64 < %s 2>&1 | FileCheck --check-prefix=CHECK-NO-SPE-EEF-ERR %s

msr PMSNEVFR_EL1, x0
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