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[AArch64][GlobalISel] Legalize more G_VECREDUCE_ADD operations. #123392

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Merged
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Jan 30, 2025
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[AArch64][GlobalISel] Legalize more G_VECREDUCE_ADD operations. #123392

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9 changes: 9 additions & 0 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3342,6 +3342,15 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
Observer.changedInstr(MI);
return Legalized;
}
case TargetOpcode::G_VECREDUCE_ADD: {
if (TypeIdx != 1)
return UnableToLegalize;
Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
widenScalarDst(MI, WideTy.getScalarType(), 0, TargetOpcode::G_TRUNC);
Observer.changedInstr(MI);
return Legalized;
}
case TargetOpcode::G_VECREDUCE_FADD:
case TargetOpcode::G_VECREDUCE_FMUL:
case TargetOpcode::G_VECREDUCE_FMIN:
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4 changes: 3 additions & 1 deletion llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
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Expand Up @@ -1215,11 +1215,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
{s32, v4s32},
{s32, v2s32},
{s64, v2s64}})
.moreElementsToNextPow2(1)
.clampMaxNumElements(1, s64, 2)
.clampMaxNumElements(1, s32, 4)
.clampMaxNumElements(1, s16, 8)
.clampMaxNumElements(1, s8, 16)
.lower();
.widenVectorEltsToVectorMinSize(1, 64)
.scalarize(1);

getActionDefinitionsBuilder({G_VECREDUCE_FMIN, G_VECREDUCE_FMAX,
G_VECREDUCE_FMINIMUM, G_VECREDUCE_FMAXIMUM})
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17 changes: 11 additions & 6 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir
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Expand Up @@ -157,12 +157,17 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[COPY]](<2 x s64>)
; CHECK-NEXT: [[VECREDUCE_ADD1:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[COPY1]](<2 x s64>)
; CHECK-NEXT: [[VECREDUCE_ADD2:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[COPY2]](<2 x s64>)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[VECREDUCE_ADD]], [[VECREDUCE_ADD1]]
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ADD]], [[VECREDUCE_ADD2]]
; CHECK-NEXT: $x0 = COPY [[ADD1]](s64)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[DEF]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[C]](s64), [[C]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[IVEC1:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[IVEC]], [[C]](s64), [[C1]](s64)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY1]]
; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY2]], [[IVEC1]]
; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[ADD]], [[ADD1]]
; CHECK-NEXT: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[ADD2]](<2 x s64>)
; CHECK-NEXT: $x0 = COPY [[VECREDUCE_ADD]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s64>) = COPY $q1
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
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Expand Up @@ -867,8 +867,8 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_VECREDUCE_ADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_VECREDUCE_MUL (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
Expand Down
99 changes: 61 additions & 38 deletions llvm/test/CodeGen/AArch64/aarch64-addv.ll
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@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64 -aarch64-neon-syntax=generic | FileCheck %s -check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64 -global-isel=1 -global-isel-abort=2 -aarch64-neon-syntax=generic 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; RUN: llc < %s -mtriple=aarch64 -aarch64-neon-syntax=generic | FileCheck %s -check-prefixes=CHECK,SDAG
; RUN: llc < %s -mtriple=aarch64 -global-isel=1 -aarch64-neon-syntax=generic | FileCheck %s --check-prefixes=CHECK,GISEL

declare i8 @llvm.vector.reduce.add.v2i8(<2 x i8>)
declare i8 @llvm.vector.reduce.add.v3i8(<3 x i8>)
Expand All @@ -22,15 +22,6 @@ declare i64 @llvm.vector.reduce.add.v3i64(<3 x i64>)
declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
declare i128 @llvm.vector.reduce.add.v2i128(<2 x i128>)

; CHECK-GI: warning: Instruction selection used fallback path for addv_v2i8
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for addv_v3i8
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for addv_v4i8
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for addv_v2i16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for addv_v3i16
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for addv_v3i32
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for addv_v3i64
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for addv_v2i128


define i8 @add_B(ptr %arr) {
; CHECK-LABEL: add_B:
Expand Down Expand Up @@ -256,15 +247,26 @@ entry:
}

define i8 @addv_v3i8(<3 x i8> %a) {
; CHECK-LABEL: addv_v3i8:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.h[0], w0
; CHECK-NEXT: mov v0.h[1], w1
; CHECK-NEXT: mov v0.h[2], w2
; CHECK-NEXT: addv h0, v0.4h
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
; SDAG-LABEL: addv_v3i8:
; SDAG: // %bb.0: // %entry
; SDAG-NEXT: movi v0.2d, #0000000000000000
; SDAG-NEXT: mov v0.h[0], w0
; SDAG-NEXT: mov v0.h[1], w1
; SDAG-NEXT: mov v0.h[2], w2
; SDAG-NEXT: addv h0, v0.4h
; SDAG-NEXT: fmov w0, s0
; SDAG-NEXT: ret
;
; GISEL-LABEL: addv_v3i8:
; GISEL: // %bb.0: // %entry
; GISEL-NEXT: fmov s0, w0
; GISEL-NEXT: mov w8, #0 // =0x0
; GISEL-NEXT: mov v0.h[1], w1
; GISEL-NEXT: mov v0.h[2], w2
; GISEL-NEXT: mov v0.h[3], w8
; GISEL-NEXT: addv h0, v0.4h
; GISEL-NEXT: fmov w0, s0
; GISEL-NEXT: ret
entry:
%arg1 = call i8 @llvm.vector.reduce.add.v3i8(<3 x i8> %a)
ret i8 %arg1
Expand Down Expand Up @@ -327,13 +329,22 @@ entry:
}

define i16 @addv_v3i16(<3 x i16> %a) {
; CHECK-LABEL: addv_v3i16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov v0.h[3], wzr
; CHECK-NEXT: addv h0, v0.4h
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
; SDAG-LABEL: addv_v3i16:
; SDAG: // %bb.0: // %entry
; SDAG-NEXT: // kill: def $d0 killed $d0 def $q0
; SDAG-NEXT: mov v0.h[3], wzr
; SDAG-NEXT: addv h0, v0.4h
; SDAG-NEXT: fmov w0, s0
; SDAG-NEXT: ret
;
; GISEL-LABEL: addv_v3i16:
; GISEL: // %bb.0: // %entry
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: mov w8, #0 // =0x0
; GISEL-NEXT: mov v0.h[3], w8
; GISEL-NEXT: addv h0, v0.4h
; GISEL-NEXT: fmov w0, s0
; GISEL-NEXT: ret
entry:
%arg1 = call i16 @llvm.vector.reduce.add.v3i16(<3 x i16> %a)
ret i16 %arg1
Expand Down Expand Up @@ -431,17 +442,29 @@ entry:
}

define i64 @addv_v3i64(<3 x i64> %a) {
; CHECK-LABEL: addv_v3i64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: mov v0.d[1], v1.d[0]
; CHECK-NEXT: mov v2.d[1], xzr
; CHECK-NEXT: add v0.2d, v0.2d, v2.2d
; CHECK-NEXT: addp d0, v0.2d
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret
; SDAG-LABEL: addv_v3i64:
; SDAG: // %bb.0: // %entry
; SDAG-NEXT: // kill: def $d2 killed $d2 def $q2
; SDAG-NEXT: // kill: def $d0 killed $d0 def $q0
; SDAG-NEXT: // kill: def $d1 killed $d1 def $q1
; SDAG-NEXT: mov v0.d[1], v1.d[0]
; SDAG-NEXT: mov v2.d[1], xzr
; SDAG-NEXT: add v0.2d, v0.2d, v2.2d
; SDAG-NEXT: addp d0, v0.2d
; SDAG-NEXT: fmov x0, d0
; SDAG-NEXT: ret
;
; GISEL-LABEL: addv_v3i64:
; GISEL: // %bb.0: // %entry
; GISEL-NEXT: // kill: def $d0 killed $d0 def $q0
; GISEL-NEXT: // kill: def $d2 killed $d2 def $q2
; GISEL-NEXT: // kill: def $d1 killed $d1 def $q1
; GISEL-NEXT: mov v0.d[1], v1.d[0]
; GISEL-NEXT: mov v2.d[1], xzr
; GISEL-NEXT: add v0.2d, v0.2d, v2.2d
; GISEL-NEXT: addp d0, v0.2d
; GISEL-NEXT: fmov x0, d0
; GISEL-NEXT: ret
entry:
%arg1 = call i64 @llvm.vector.reduce.add.v3i64(<3 x i64> %a)
ret i64 %arg1
Expand Down
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