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[AMDGPU] Reject misaligned SGPR constraints for inline asm #123590

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Merged
merged 3 commits into from
Jan 20, 2025
Merged

[AMDGPU] Reject misaligned SGPR constraints for inline asm #123590

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9b8bee2
[AMDGPU] Reject misaligned SGPR constraints for inline asm
ritter-x2a Jan 20, 2025
19512cb
Update llvm/lib/Target/AMDGPU/SIISelLowering.cpp
ritter-x2a Jan 20, 2025
a7e5a7c
Update llvm/lib/Target/AMDGPU/SIISelLowering.cpp
ritter-x2a Jan 20, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -15877,7 +15877,7 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
RC = TRI->getAGPRClassForBitWidth(Width);
if (RC) {
Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0, RC);
if (Reg == 0U) {
if (!Reg ) {
// The register class does not contain the requested register,
// e.g., because it is an SGPR pair that would violate alignment
// requirements.
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