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[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM #123592

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Merged
merged 2 commits into from
Jan 21, 2025
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[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM #123592

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860cf3a
[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM
optimisan Jan 20, 2025
0590605
add missing header
optimisan Jan 21, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPU.h
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Expand Up @@ -177,7 +177,7 @@ extern char &SIShrinkInstructionsLegacyID;
void initializeSIFixSGPRCopiesLegacyPass(PassRegistry &);
extern char &SIFixSGPRCopiesLegacyID;

void initializeSIFixVGPRCopiesPass(PassRegistry &);
void initializeSIFixVGPRCopiesLegacyPass(PassRegistry &);
extern char &SIFixVGPRCopiesID;

void initializeSILowerWWMCopiesPass(PassRegistry &);
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1 change: 1 addition & 0 deletions llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
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Expand Up @@ -99,6 +99,7 @@ FUNCTION_PASS_WITH_PARAMS(
MACHINE_FUNCTION_PASS("amdgpu-isel", AMDGPUISelDAGToDAGPass(*this))
MACHINE_FUNCTION_PASS("si-fix-sgpr-copies", SIFixSGPRCopiesPass())
MACHINE_FUNCTION_PASS("si-i1-copies", SILowerI1CopiesPass())
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@cdevadas cdevadas Jan 20, 2025

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Unrelated to this patch. This option is placed wrongly. Should have a post patch to sink it down.

MACHINE_FUNCTION_PASS("si-fix-vgpr-copies", SIFixVGPRCopiesPass())
MACHINE_FUNCTION_PASS("si-fold-operands", SIFoldOperandsPass());
MACHINE_FUNCTION_PASS("gcn-dpp-combine", GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-load-store-opt", SILoadStoreOptimizerPass())
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5 changes: 3 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
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Expand Up @@ -36,6 +36,7 @@
#include "R600.h"
#include "R600TargetMachine.h"
#include "SIFixSGPRCopies.h"
#include "SIFixVGPRCopies.h"
#include "SIFoldOperands.h"
#include "SILoadStoreOptimizer.h"
#include "SILowerControlFlow.h"
Expand Down Expand Up @@ -486,7 +487,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeAMDGPUMarkLastScratchLoadPass(*PR);
initializeSILowerSGPRSpillsLegacyPass(*PR);
initializeSIFixSGPRCopiesLegacyPass(*PR);
initializeSIFixVGPRCopiesPass(*PR);
initializeSIFixVGPRCopiesLegacyPass(*PR);
initializeSIFoldOperandsLegacyPass(*PR);
initializeSIPeepholeSDWALegacyPass(*PR);
initializeSIShrinkInstructionsLegacyPass(*PR);
Expand Down Expand Up @@ -2107,7 +2108,7 @@ void AMDGPUCodeGenPassBuilder::addMachineSSAOptimization(
}

void AMDGPUCodeGenPassBuilder::addPostRegAlloc(AddMachinePass &addPass) const {
// addPass(SIFixVGPRCopiesID);
addPass(SIFixVGPRCopiesPass());
if (TM.getOptLevel() > CodeGenOptLevel::None)
addPass(SIOptimizeExecMaskingPass());
Base::addPostRegAlloc(addPass);
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32 changes: 24 additions & 8 deletions llvm/lib/Target/AMDGPU/SIFixVGPRCopies.cpp
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Expand Up @@ -11,6 +11,7 @@
///
//===----------------------------------------------------------------------===//

#include "SIFixVGPRCopies.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
Expand All @@ -22,13 +23,12 @@ using namespace llvm;

namespace {

class SIFixVGPRCopies : public MachineFunctionPass {
class SIFixVGPRCopiesLegacy : public MachineFunctionPass {
public:
static char ID;

public:
SIFixVGPRCopies() : MachineFunctionPass(ID) {
initializeSIFixVGPRCopiesPass(*PassRegistry::getPassRegistry());
SIFixVGPRCopiesLegacy() : MachineFunctionPass(ID) {
initializeSIFixVGPRCopiesLegacyPass(*PassRegistry::getPassRegistry());
}

void getAnalysisUsage(AnalysisUsage &AU) const override {
Expand All @@ -41,15 +41,31 @@ class SIFixVGPRCopies : public MachineFunctionPass {
StringRef getPassName() const override { return "SI Fix VGPR copies"; }
};

class SIFixVGPRCopies {
public:
bool run(MachineFunction &MF);
};

} // End anonymous namespace.

INITIALIZE_PASS(SIFixVGPRCopies, DEBUG_TYPE, "SI Fix VGPR copies", false, false)
INITIALIZE_PASS(SIFixVGPRCopiesLegacy, DEBUG_TYPE, "SI Fix VGPR copies", false,
false)

char SIFixVGPRCopies::ID = 0;
char SIFixVGPRCopiesLegacy::ID = 0;

char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID;
char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopiesLegacy::ID;

PreservedAnalyses SIFixVGPRCopiesPass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &) {
SIFixVGPRCopies().run(MF);
return PreservedAnalyses::all();
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@jayfoad jayfoad Jan 20, 2025

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Why is it OK to return all unconditionally?

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@arsenm arsenm Jan 20, 2025 •
edited
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the legacy one does setPreservesAll, so this is just replicating that

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@jayfoad jayfoad Jan 20, 2025

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Ack. (s/DAG/legacy/?)

}

bool SIFixVGPRCopiesLegacy::runOnMachineFunction(MachineFunction &MF) {
return SIFixVGPRCopies().run(MF);
}

bool SIFixVGPRCopies::runOnMachineFunction(MachineFunction &MF) {
bool SIFixVGPRCopies::run(MachineFunction &MF) {
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
const SIRegisterInfo *TRI = ST.getRegisterInfo();
const SIInstrInfo *TII = ST.getInstrInfo();
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22 changes: 22 additions & 0 deletions llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
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@@ -0,0 +1,22 @@
//===- SIFixVGPRCopies.h ----------------------------------------*- C++- *-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_LIB_TARGET_AMDGPU_SIFIXVGPRCOPIES_H
#define LLVM_LIB_TARGET_AMDGPU_SIFIXVGPRCOPIES_H

#include "llvm/CodeGen/MachinePassManager.h"

namespace llvm {
class SIFixVGPRCopiesPass : public PassInfoMixin<SIFixVGPRCopiesPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
};
} // namespace llvm

#endif // LLVM_LIB_TARGET_AMDGPU_SIFIXVGPRCOPIES_H
2 changes: 2 additions & 0 deletions llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir
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@@ -1,4 +1,6 @@
# RUN: llc -mtriple=amdgcn -start-after=greedy -disable-copyprop -stop-after=si-optimize-exec-masking -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgcn -passes=si-fix-vgpr-copies,si-optimize-exec-masking -o - %s | FileCheck %s

# Check that we first do all vector instructions and only then change exec
# CHECK-DAG: COPY $vgpr10_vgpr11
# CHECK-DAG: COPY $vgpr12_vgpr13
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