Skip to content

Allow more dead AND operations to be eliminated #123686

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
wants to merge 1 commit into from
Closed

Allow more dead AND operations to be eliminated #123686

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1429,8 +1429,8 @@ bool TargetLowering::SimplifyDemandedBits(
// Do not increment Depth here; that can cause an infinite loop.
KnownBits LHSKnown = TLO.DAG.computeKnownBits(Op0, DemandedElts, Depth);
// If the LHS already has zeros where RHSC does, this 'and' is dead.
if ((LHSKnown.Zero & DemandedBits) ==
(~RHSC->getAPIntValue() & DemandedBits))

if (DemandedBits.isSubsetOf(LHSKnown.Zero | RHSC->getAPIntValue()))
return TLO.CombineTo(Op, Op0);

// If any of the set bits in the RHS are known zero on the LHS, shrink
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/fabs.f16.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -668,7 +668,7 @@ define amdgpu_kernel void @v_extract_fabs_no_fold_v2f16(ptr addrspace(1) %in) #0
; CI-NEXT: flat_load_dword v0, v[0:1]
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_bfe_u32 v1, v0, 16, 15
; CI-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; CI-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
Copy link
Contributor

@arsenm arsenm Jan 21, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Technically no worse but now we're emitting a messier constant

; CI-NEXT: flat_store_short v[0:1], v0
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: flat_store_short v[0:1], v1
Expand Down
8 changes: 5 additions & 3 deletions llvm/test/CodeGen/ARM/popcnt.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -311,10 +311,12 @@ define i32 @ctpop16(i16 %x) nounwind readnone {
; CHECK-NEXT: and r2, r0, r1
; CHECK-NEXT: and r0, r1, r0, lsr #2
; CHECK-NEXT: add r0, r2, r0
; CHECK-NEXT: mov r1, #15
; CHECK-NEXT: orr r1, r1, #3840
; CHECK-NEXT: add r0, r0, r0, lsr #4
; CHECK-NEXT: and r1, r0, #3840
; CHECK-NEXT: and r0, r0, #15
; CHECK-NEXT: add r0, r0, r1, lsr #8
; CHECK-NEXT: and r0, r0, r1
Copy link
Contributor

@arsenm arsenm Jan 21, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Regression

; CHECK-NEXT: add r0, r0, r0, lsr #8
; CHECK-NEXT: and r0, r0, #255
; CHECK-NEXT: mov pc, lr
%count = tail call i16 @llvm.ctpop.i16(i16 %x)
%conv = zext i16 %count to i32
Expand Down
5 changes: 3 additions & 2 deletions llvm/test/CodeGen/LoongArch/ctlz-cttz-ctpop.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -201,9 +201,10 @@ define i16 @test_ctpop_i16(i16 %a) nounwind {
; LA32-NEXT: add.w $a0, $a2, $a0
; LA32-NEXT: srli.w $a1, $a0, 4
; LA32-NEXT: add.w $a0, $a0, $a1
; LA32-NEXT: bstrpick.w $a1, $a0, 11, 8
; LA32-NEXT: andi $a0, $a0, 15
; LA32-NEXT: andi $a0, $a0, 3855
; LA32-NEXT: srli.w $a1, $a0, 8
Copy link
Contributor

@arsenm arsenm Jan 21, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Regression

; LA32-NEXT: add.w $a0, $a0, $a1
; LA32-NEXT: andi $a0, $a0, 31
; LA32-NEXT: ret
;
; LA64-LABEL: test_ctpop_i16:
Expand Down
9 changes: 5 additions & 4 deletions llvm/test/CodeGen/PowerPC/popcnt-zext.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,9 @@ define i16 @zpop_i8_i16(i8 %x) {
; SLOW-NEXT: srwi 4, 3, 4
; SLOW-NEXT: add 3, 3, 4
; SLOW-NEXT: rlwinm 4, 3, 24, 28, 31
; SLOW-NEXT: clrlwi 3, 3, 28
; SLOW-NEXT: andi. 3, 3, 3855
; SLOW-NEXT: add 3, 3, 4
; SLOW-NEXT: clrlwi 3, 3, 27
Copy link
Contributor

@arsenm arsenm Jan 21, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Regression

; SLOW-NEXT: blr
%z = zext i8 %x to i16
%pop = tail call i16 @llvm.ctpop.i16(i16 %z)
Expand Down Expand Up @@ -173,9 +174,9 @@ define i32 @popz_i16_32(i16 %x) {
; SLOW-NEXT: srwi 4, 3, 4
; SLOW-NEXT: add 3, 3, 4
; SLOW-NEXT: rlwinm 4, 3, 24, 28, 31
; SLOW-NEXT: clrlwi 3, 3, 28
; SLOW-NEXT: andi. 3, 3, 3855
; SLOW-NEXT: add 3, 3, 4
; SLOW-NEXT: clrldi 3, 3, 32
; SLOW-NEXT: clrlwi 3, 3, 27
; SLOW-NEXT: blr
%pop = tail call i16 @llvm.ctpop.i16(i16 %x)
%z = zext i16 %pop to i32
Expand Down Expand Up @@ -278,7 +279,7 @@ define i64 @popa_i16_i64(i16 %x) {
; SLOW-NEXT: srwi 4, 3, 4
; SLOW-NEXT: add 3, 3, 4
; SLOW-NEXT: rlwinm 4, 3, 24, 28, 31
; SLOW-NEXT: clrlwi 3, 3, 28
; SLOW-NEXT: andi. 3, 3, 3855
; SLOW-NEXT: add 3, 3, 4
; SLOW-NEXT: rlwinm 3, 3, 0, 27, 27
; SLOW-NEXT: blr
Expand Down
114 changes: 70 additions & 44 deletions llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -142,13 +142,15 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32_NOZBB-NEXT: and a1, a0, a2
; RV32_NOZBB-NEXT: srli a0, a0, 2
; RV32_NOZBB-NEXT: and a0, a0, a2
; RV32_NOZBB-NEXT: lui a2, 1
; RV32_NOZBB-NEXT: add a0, a1, a0
; RV32_NOZBB-NEXT: srli a1, a0, 4
; RV32_NOZBB-NEXT: add a0, a0, a1
; RV32_NOZBB-NEXT: andi a1, a0, 15
; RV32_NOZBB-NEXT: slli a0, a0, 20
; RV32_NOZBB-NEXT: srli a0, a0, 28
; RV32_NOZBB-NEXT: add a0, a1, a0
; RV32_NOZBB-NEXT: addi a1, a2, -241
; RV32_NOZBB-NEXT: and a0, a0, a1
; RV32_NOZBB-NEXT: srli a1, a0, 8
; RV32_NOZBB-NEXT: add a0, a0, a1
; RV32_NOZBB-NEXT: andi a0, a0, 31
; RV32_NOZBB-NEXT: ret
; RV32_NOZBB-NEXT: .LBB1_2:
; RV32_NOZBB-NEXT: li a0, 16
Expand All @@ -172,13 +174,15 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV64NOZBB-NEXT: and a1, a0, a2
; RV64NOZBB-NEXT: srli a0, a0, 2
; RV64NOZBB-NEXT: and a0, a0, a2
; RV64NOZBB-NEXT: lui a2, 1
; RV64NOZBB-NEXT: add a0, a1, a0
; RV64NOZBB-NEXT: srli a1, a0, 4
; RV64NOZBB-NEXT: add a0, a0, a1
; RV64NOZBB-NEXT: andi a1, a0, 15
; RV64NOZBB-NEXT: slli a0, a0, 52
; RV64NOZBB-NEXT: srli a0, a0, 60
; RV64NOZBB-NEXT: add a0, a1, a0
; RV64NOZBB-NEXT: addiw a1, a2, -241
; RV64NOZBB-NEXT: and a0, a0, a1
; RV64NOZBB-NEXT: srli a1, a0, 8
; RV64NOZBB-NEXT: add a0, a0, a1
; RV64NOZBB-NEXT: andi a0, a0, 31
; RV64NOZBB-NEXT: ret
; RV64NOZBB-NEXT: .LBB1_2:
; RV64NOZBB-NEXT: li a0, 16
Expand Down Expand Up @@ -631,13 +635,15 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV32_NOZBB-NEXT: and a1, a0, a2
; RV32_NOZBB-NEXT: srli a0, a0, 2
; RV32_NOZBB-NEXT: and a0, a0, a2
; RV32_NOZBB-NEXT: lui a2, 1
; RV32_NOZBB-NEXT: add a0, a1, a0
; RV32_NOZBB-NEXT: srli a1, a0, 4
; RV32_NOZBB-NEXT: add a0, a0, a1
; RV32_NOZBB-NEXT: andi a1, a0, 15
; RV32_NOZBB-NEXT: slli a0, a0, 20
; RV32_NOZBB-NEXT: srli a0, a0, 28
; RV32_NOZBB-NEXT: add a0, a1, a0
; RV32_NOZBB-NEXT: addi a1, a2, -241
; RV32_NOZBB-NEXT: and a0, a0, a1
; RV32_NOZBB-NEXT: srli a1, a0, 8
; RV32_NOZBB-NEXT: add a0, a0, a1
; RV32_NOZBB-NEXT: andi a0, a0, 31
; RV32_NOZBB-NEXT: ret
;
; RV64NOZBB-LABEL: test_cttz_i16_zero_undef:
Expand All @@ -655,13 +661,15 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV64NOZBB-NEXT: and a1, a0, a2
; RV64NOZBB-NEXT: srli a0, a0, 2
; RV64NOZBB-NEXT: and a0, a0, a2
; RV64NOZBB-NEXT: lui a2, 1
; RV64NOZBB-NEXT: add a0, a1, a0
; RV64NOZBB-NEXT: srli a1, a0, 4
; RV64NOZBB-NEXT: add a0, a0, a1
; RV64NOZBB-NEXT: andi a1, a0, 15
; RV64NOZBB-NEXT: slli a0, a0, 52
; RV64NOZBB-NEXT: srli a0, a0, 60
; RV64NOZBB-NEXT: add a0, a1, a0
; RV64NOZBB-NEXT: addiw a1, a2, -241
; RV64NOZBB-NEXT: and a0, a0, a1
; RV64NOZBB-NEXT: srli a1, a0, 8
; RV64NOZBB-NEXT: add a0, a0, a1
; RV64NOZBB-NEXT: andi a0, a0, 31
; RV64NOZBB-NEXT: ret
;
; RV32ZBB-LABEL: test_cttz_i16_zero_undef:
Expand Down Expand Up @@ -1073,13 +1081,15 @@ define i16 @test_ctlz_i16(i16 %a) nounwind {
; RV32_NOZBB-NEXT: and a1, a0, a2
; RV32_NOZBB-NEXT: srli a0, a0, 2
; RV32_NOZBB-NEXT: and a0, a0, a2
; RV32_NOZBB-NEXT: lui a2, 1
; RV32_NOZBB-NEXT: add a0, a1, a0
; RV32_NOZBB-NEXT: srli a1, a0, 4
; RV32_NOZBB-NEXT: add a0, a0, a1
; RV32_NOZBB-NEXT: andi a1, a0, 15
; RV32_NOZBB-NEXT: slli a0, a0, 20
; RV32_NOZBB-NEXT: srli a0, a0, 28
; RV32_NOZBB-NEXT: add a0, a1, a0
; RV32_NOZBB-NEXT: addi a1, a2, -241
; RV32_NOZBB-NEXT: and a0, a0, a1
; RV32_NOZBB-NEXT: srli a1, a0, 8
; RV32_NOZBB-NEXT: add a0, a0, a1
; RV32_NOZBB-NEXT: andi a0, a0, 31
; RV32_NOZBB-NEXT: ret
; RV32_NOZBB-NEXT: .LBB9_2:
; RV32_NOZBB-NEXT: li a0, 16
Expand Down Expand Up @@ -1112,13 +1122,15 @@ define i16 @test_ctlz_i16(i16 %a) nounwind {
; RV64NOZBB-NEXT: and a1, a0, a2
; RV64NOZBB-NEXT: srli a0, a0, 2
; RV64NOZBB-NEXT: and a0, a0, a2
; RV64NOZBB-NEXT: lui a2, 1
; RV64NOZBB-NEXT: add a0, a1, a0
; RV64NOZBB-NEXT: srli a1, a0, 4
; RV64NOZBB-NEXT: add a0, a0, a1
; RV64NOZBB-NEXT: andi a1, a0, 15
; RV64NOZBB-NEXT: slli a0, a0, 52
; RV64NOZBB-NEXT: srli a0, a0, 60
; RV64NOZBB-NEXT: add a0, a1, a0
; RV64NOZBB-NEXT: addiw a1, a2, -241
; RV64NOZBB-NEXT: and a0, a0, a1
; RV64NOZBB-NEXT: srli a1, a0, 8
; RV64NOZBB-NEXT: add a0, a0, a1
; RV64NOZBB-NEXT: andi a0, a0, 31
; RV64NOZBB-NEXT: ret
; RV64NOZBB-NEXT: .LBB9_2:
; RV64NOZBB-NEXT: li a0, 16
Expand Down Expand Up @@ -1722,13 +1734,15 @@ define i16 @test_ctlz_i16_zero_undef(i16 %a) nounwind {
; RV32_NOZBB-NEXT: and a1, a0, a2
; RV32_NOZBB-NEXT: srli a0, a0, 2
; RV32_NOZBB-NEXT: and a0, a0, a2
; RV32_NOZBB-NEXT: lui a2, 1
; RV32_NOZBB-NEXT: add a0, a1, a0
; RV32_NOZBB-NEXT: srli a1, a0, 4
; RV32_NOZBB-NEXT: add a0, a0, a1
; RV32_NOZBB-NEXT: andi a1, a0, 15
; RV32_NOZBB-NEXT: slli a0, a0, 20
; RV32_NOZBB-NEXT: srli a0, a0, 28
; RV32_NOZBB-NEXT: add a0, a1, a0
; RV32_NOZBB-NEXT: addi a1, a2, -241
; RV32_NOZBB-NEXT: and a0, a0, a1
; RV32_NOZBB-NEXT: srli a1, a0, 8
; RV32_NOZBB-NEXT: add a0, a0, a1
; RV32_NOZBB-NEXT: andi a0, a0, 31
; RV32_NOZBB-NEXT: ret
;
; RV64NOZBB-LABEL: test_ctlz_i16_zero_undef:
Expand Down Expand Up @@ -1756,13 +1770,15 @@ define i16 @test_ctlz_i16_zero_undef(i16 %a) nounwind {
; RV64NOZBB-NEXT: and a1, a0, a2
; RV64NOZBB-NEXT: srli a0, a0, 2
; RV64NOZBB-NEXT: and a0, a0, a2
; RV64NOZBB-NEXT: lui a2, 1
; RV64NOZBB-NEXT: add a0, a1, a0
; RV64NOZBB-NEXT: srli a1, a0, 4
; RV64NOZBB-NEXT: add a0, a0, a1
; RV64NOZBB-NEXT: andi a1, a0, 15
; RV64NOZBB-NEXT: slli a0, a0, 52
; RV64NOZBB-NEXT: srli a0, a0, 60
; RV64NOZBB-NEXT: add a0, a1, a0
; RV64NOZBB-NEXT: addiw a1, a2, -241
; RV64NOZBB-NEXT: and a0, a0, a1
; RV64NOZBB-NEXT: srli a1, a0, 8
; RV64NOZBB-NEXT: add a0, a0, a1
; RV64NOZBB-NEXT: andi a0, a0, 31
; RV64NOZBB-NEXT: ret
;
; RV32ZBB-LABEL: test_ctlz_i16_zero_undef:
Expand Down Expand Up @@ -2310,13 +2326,15 @@ define i16 @test_ctpop_i16(i16 %a) nounwind {
; RV32_NOZBB-NEXT: and a1, a0, a2
; RV32_NOZBB-NEXT: srli a0, a0, 2
; RV32_NOZBB-NEXT: and a0, a0, a2
; RV32_NOZBB-NEXT: lui a2, 1
; RV32_NOZBB-NEXT: add a0, a1, a0
; RV32_NOZBB-NEXT: srli a1, a0, 4
; RV32_NOZBB-NEXT: add a0, a0, a1
; RV32_NOZBB-NEXT: andi a1, a0, 15
; RV32_NOZBB-NEXT: slli a0, a0, 20
; RV32_NOZBB-NEXT: srli a0, a0, 28
; RV32_NOZBB-NEXT: add a0, a1, a0
; RV32_NOZBB-NEXT: addi a1, a2, -241
; RV32_NOZBB-NEXT: and a0, a0, a1
; RV32_NOZBB-NEXT: srli a1, a0, 8
; RV32_NOZBB-NEXT: add a0, a0, a1
; RV32_NOZBB-NEXT: andi a0, a0, 31
; RV32_NOZBB-NEXT: ret
;
; RV64NOZBB-LABEL: test_ctpop_i16:
Expand All @@ -2331,13 +2349,15 @@ define i16 @test_ctpop_i16(i16 %a) nounwind {
; RV64NOZBB-NEXT: and a1, a0, a2
; RV64NOZBB-NEXT: srli a0, a0, 2
; RV64NOZBB-NEXT: and a0, a0, a2
; RV64NOZBB-NEXT: lui a2, 1
; RV64NOZBB-NEXT: add a0, a1, a0
; RV64NOZBB-NEXT: srli a1, a0, 4
; RV64NOZBB-NEXT: add a0, a0, a1
; RV64NOZBB-NEXT: andi a1, a0, 15
; RV64NOZBB-NEXT: slli a0, a0, 52
; RV64NOZBB-NEXT: srli a0, a0, 60
; RV64NOZBB-NEXT: add a0, a1, a0
; RV64NOZBB-NEXT: addiw a1, a2, -241
; RV64NOZBB-NEXT: and a0, a0, a1
; RV64NOZBB-NEXT: srli a1, a0, 8
; RV64NOZBB-NEXT: add a0, a0, a1
; RV64NOZBB-NEXT: andi a0, a0, 31
; RV64NOZBB-NEXT: ret
;
; RV32ZBB-LABEL: test_ctpop_i16:
Expand All @@ -2364,12 +2384,15 @@ define i16 @test_ctpop_i16(i16 %a) nounwind {
; RV32XTHEADBB-NEXT: and a1, a0, a2
; RV32XTHEADBB-NEXT: srli a0, a0, 2
; RV32XTHEADBB-NEXT: and a0, a0, a2
; RV32XTHEADBB-NEXT: lui a2, 1
; RV32XTHEADBB-NEXT: add a0, a1, a0
; RV32XTHEADBB-NEXT: srli a1, a0, 4
; RV32XTHEADBB-NEXT: add a0, a0, a1
; RV32XTHEADBB-NEXT: th.extu a1, a0, 11, 8
; RV32XTHEADBB-NEXT: andi a0, a0, 15
; RV32XTHEADBB-NEXT: addi a1, a2, -241
; RV32XTHEADBB-NEXT: and a0, a0, a1
; RV32XTHEADBB-NEXT: srli a1, a0, 8
; RV32XTHEADBB-NEXT: add a0, a0, a1
; RV32XTHEADBB-NEXT: andi a0, a0, 31
; RV32XTHEADBB-NEXT: ret
;
; RV64XTHEADBB-LABEL: test_ctpop_i16:
Expand All @@ -2384,12 +2407,15 @@ define i16 @test_ctpop_i16(i16 %a) nounwind {
; RV64XTHEADBB-NEXT: and a1, a0, a2
; RV64XTHEADBB-NEXT: srli a0, a0, 2
; RV64XTHEADBB-NEXT: and a0, a0, a2
; RV64XTHEADBB-NEXT: lui a2, 1
; RV64XTHEADBB-NEXT: add a0, a1, a0
; RV64XTHEADBB-NEXT: srli a1, a0, 4
; RV64XTHEADBB-NEXT: add a0, a0, a1
; RV64XTHEADBB-NEXT: th.extu a1, a0, 11, 8
; RV64XTHEADBB-NEXT: andi a0, a0, 15
; RV64XTHEADBB-NEXT: addiw a1, a2, -241
; RV64XTHEADBB-NEXT: and a0, a0, a1
; RV64XTHEADBB-NEXT: srli a1, a0, 8
; RV64XTHEADBB-NEXT: add a0, a0, a1
; RV64XTHEADBB-NEXT: andi a0, a0, 31
; RV64XTHEADBB-NEXT: ret
%1 = call i16 @llvm.ctpop.i16(i16 %a)
ret i16 %1
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2636,7 +2636,7 @@ define <16 x i8> @buildvec_v16i8_undef_edges(ptr %p) {
; RVA22U64-NEXT: or a0, a0, a5
; RVA22U64-NEXT: slli a6, a6, 24
; RVA22U64-NEXT: or a2, a2, a4
; RVA22U64-NEXT: add.uw a2, a6, a2
; RVA22U64-NEXT: or a2, a6, a2
; RVA22U64-NEXT: or a0, a0, a1
; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RVA22U64-NEXT: vmv.v.x v8, a2
Expand Down
Loading
Loading