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[CodeGen] Use MCRegister instead of MCPhysReg in RegisterMaskPair. NFC #123688

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Merged
topperc merged 1 commit into from
Jan 21, 2025
Merged

[CodeGen] Use MCRegister instead of MCPhysReg in RegisterMaskPair. NFC #123688

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2 changes: 1 addition & 1 deletion llvm/include/llvm/CodeGen/MachineBasicBlock.h
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Original file line number Diff line number Diff line change
Expand Up @@ -129,7 +129,7 @@ class MachineBasicBlock
/// clearly as they both have an integer type.
struct RegisterMaskPair {
public:
MCPhysReg PhysReg;
MCRegister PhysReg;
LaneBitmask LaneMask;

RegisterMaskPair(MCPhysReg PhysReg, LaneBitmask LaneMask)
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/BranchFolding.cpp
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Expand Up @@ -381,7 +381,7 @@ void BranchFolder::replaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
// full registers:
assert(P.LaneMask == LaneBitmask::getAll() &&
"Can only handle full register.");
MCPhysReg Reg = P.PhysReg;
MCRegister Reg = P.PhysReg;
if (!LiveRegs.available(*MRI, Reg))
continue;
DebugLoc DL;
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/LivePhysRegs.cpp
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Expand Up @@ -154,7 +154,7 @@ bool LivePhysRegs::available(const MachineRegisterInfo &MRI,
/// Add live-in registers of basic block \p MBB to \p LiveRegs.
void LivePhysRegs::addBlockLiveIns(const MachineBasicBlock &MBB) {
for (const auto &LI : MBB.liveins()) {
MCPhysReg Reg = LI.PhysReg;
MCRegister Reg = LI.PhysReg;
LaneBitmask Mask = LI.LaneMask;
MCSubRegIndexIterator S(Reg, TRI);
assert(Mask.any() && "Invalid livein mask");
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/LiveVariables.cpp
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Expand Up @@ -576,7 +576,7 @@ void LiveVariables::runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs) {
// Mark live-in registers as live-in.
SmallVector<Register, 4> Defs;
for (const auto &LI : MBB->liveins()) {
assert(Register::isPhysicalRegister(LI.PhysReg) &&
assert(LI.PhysReg.isPhysical() &&
"Cannot have a live-in virtual register!");
HandlePhysRegDef(LI.PhysReg, nullptr, Defs);
}
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4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/MachineVerifier.cpp
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Expand Up @@ -894,7 +894,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
regsLive.clear();
if (MRI->tracksLiveness()) {
for (const auto &LI : MBB->liveins()) {
if (!Register::isPhysicalRegister(LI.PhysReg)) {
if (!LI.PhysReg.isPhysical()) {
report("MBB live-in list contains non-physical register", MBB);
continue;
}
Expand Down Expand Up @@ -3448,7 +3448,7 @@ void MachineVerifier::visitMachineFunctionAfter() {
if (MRI->tracksLiveness())
for (const auto &MBB : *MF)
for (MachineBasicBlock::RegisterMaskPair P : MBB.liveins()) {
MCPhysReg LiveInReg = P.PhysReg;
MCRegister LiveInReg = P.PhysReg;
bool hasAliases = MCRegAliasIterator(LiveInReg, TRI, false).isValid();
if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
continue;
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4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/RDFLiveness.cpp
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Expand Up @@ -895,7 +895,7 @@ void Liveness::computeLiveIns() {
void Liveness::resetLiveIns() {
for (auto &B : DFG.getMF()) {
// Remove all live-ins.
std::vector<unsigned> T;
std::vector<MCRegister> T;
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@arsenm arsenm Jan 21, 2025

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This probably should be MCPhysReg

for (const MachineBasicBlock::RegisterMaskPair &LI : B.liveins())
T.push_back(LI.PhysReg);
for (auto I : T)
Expand All @@ -917,7 +917,7 @@ void Liveness::resetKills(MachineBasicBlock *B) {
for (auto I : B->liveins()) {
MCSubRegIndexIterator S(I.PhysReg, &TRI);
if (!S.isValid()) {
LV.set(I.PhysReg);
LV.set(I.PhysReg.id());
continue;
}
do {
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6 changes: 3 additions & 3 deletions llvm/lib/CodeGen/RegAllocFast.cpp
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Expand Up @@ -276,7 +276,7 @@ class RegAllocFastImpl {
// Assign index for each instruction to quickly determine dominance.
InstrPosIndexes PosIndexes;

void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
void setPhysRegState(MCRegister PhysReg, unsigned NewState);
bool isPhysRegFree(MCPhysReg PhysReg) const;

/// Mark a physreg as used in this instruction.
Expand Down Expand Up @@ -449,7 +449,7 @@ bool RegAllocFastImpl::shouldAllocateRegister(const Register Reg) const {
return ShouldAllocateRegisterImpl(*TRI, *MRI, Reg);
}

void RegAllocFastImpl::setPhysRegState(MCPhysReg PhysReg, unsigned NewState) {
void RegAllocFastImpl::setPhysRegState(MCRegister PhysReg, unsigned NewState) {
for (MCRegUnit Unit : TRI->regunits(PhysReg))
RegUnitStates[Unit] = NewState;
}
Expand Down Expand Up @@ -671,7 +671,7 @@ void RegAllocFastImpl::reloadAtBegin(MachineBasicBlock &MBB) {
return;

for (MachineBasicBlock::RegisterMaskPair P : MBB.liveins()) {
MCPhysReg Reg = P.PhysReg;
MCRegister Reg = P.PhysReg;
// Set state to live-in. This possibly overrides mappings to virtual
// registers but we don't care anymore at this point.
setPhysRegState(Reg, regLiveIn);
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
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Expand Up @@ -251,7 +251,7 @@ static bool supportLoadFromLiteral(const MachineInstr &MI) {
/// Number of GPR registers traked by mapRegToGPRIndex()
static const unsigned N_GPR_REGS = 31;
/// Map register number to index from 0-30.
static int mapRegToGPRIndex(MCPhysReg Reg) {
static int mapRegToGPRIndex(MCRegister Reg) {
static_assert(AArch64::X28 - AArch64::X0 + 3 == N_GPR_REGS, "Number of GPRs");
static_assert(AArch64::W30 - AArch64::W0 + 1 == N_GPR_REGS, "Number of GPRs");
if (AArch64::X0 <= Reg && Reg <= AArch64::X28)
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2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
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Expand Up @@ -402,7 +402,7 @@ void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB,
for (const MachineBasicBlock *S : MBB.successors())
if (S != &SuccBB)
for (const auto &LI : S->liveins())
Uses.set(LI.PhysReg);
Uses.set(LI.PhysReg.id());
}

bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) {
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2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/X86FrameLowering.cpp
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Expand Up @@ -174,7 +174,7 @@ static unsigned getPOP2Opcode(const X86Subtarget &ST) {

static bool isEAXLiveIn(MachineBasicBlock &MBB) {
for (MachineBasicBlock::RegisterMaskPair RegMask : MBB.liveins()) {
unsigned Reg = RegMask.PhysReg;
MCRegister Reg = RegMask.PhysReg;

if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
Reg == X86::AH || Reg == X86::AL)
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