[AMDGPU][NewPM] Port SIPostRABundler to NPM

llvm/lib/Target/AMDGPU/AMDGPU.h

@@ -428,8 +428,8 @@ extern char &SIInsertWaitcntsID;
 void initializeSIFormMemoryClausesLegacyPass(PassRegistry &);
 extern char &SIFormMemoryClausesID;
 
-void initializeSIPostRABundlerPass(PassRegistry&);
-extern char &SIPostRABundlerID;
+void initializeSIPostRABundlerLegacyPass(PassRegistry &);
+extern char &SIPostRABundlerLegacyID;
 
 void initializeGCNCreateVOPDPass(PassRegistry &);
 extern char &GCNCreateVOPDID;

llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def

@@ -114,6 +114,7 @@ MACHINE_FUNCTION_PASS("si-lower-wwm-copies", SILowerWWMCopiesPass())
 MACHINE_FUNCTION_PASS("si-opt-vgpr-liverange", SIOptimizeVGPRLiveRangePass())
 MACHINE_FUNCTION_PASS("si-optimize-exec-masking", SIOptimizeExecMaskingPass())
 MACHINE_FUNCTION_PASS("si-peephole-sdwa", SIPeepholeSDWAPass())
+MACHINE_FUNCTION_PASS("si-post-ra-bundler", SIPostRABundlerPass())
 MACHINE_FUNCTION_PASS("si-pre-allocate-wwm-regs", SIPreAllocateWWMRegsPass())
 MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
 MACHINE_FUNCTION_PASS("si-wqm", SIWholeQuadModePass())

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

@@ -53,6 +53,7 @@
 #include "SIOptimizeExecMasking.h"
 #include "SIOptimizeVGPRLiveRange.h"
 #include "SIPeepholeSDWA.h"
+#include "SIPostRABundler.h"
 #include "SIPreAllocateWWMRegs.h"
 #include "SIShrinkInstructions.h"
 #include "SIWholeQuadMode.h"
@@ -543,7 +544,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
   initializeSIOptimizeExecMaskingLegacyPass(*PR);
   initializeSIPreAllocateWWMRegsLegacyPass(*PR);
   initializeSIFormMemoryClausesLegacyPass(*PR);
-  initializeSIPostRABundlerPass(*PR);
+  initializeSIPostRABundlerLegacyPass(*PR);
   initializeGCNCreateVOPDPass(*PR);
   initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
   initializeAMDGPUAAWrapperPassPass(*PR);
@@ -1657,7 +1658,7 @@ void GCNPassConfig::addPostRegAlloc() {
 void GCNPassConfig::addPreSched2() {
   if (TM->getOptLevel() > CodeGenOptLevel::None)
     addPass(createSIShrinkInstructionsLegacyPass());
-  addPass(&SIPostRABundlerID);
+  addPass(&SIPostRABundlerLegacyID);
 }
 
 void GCNPassConfig::addPreEmitPass() {

llvm/lib/Target/AMDGPU/SIPostRABundler.cpp

@@ -12,6 +12,7 @@
 ///
 //===----------------------------------------------------------------------===//
 
+#include "SIPostRABundler.h"
 #include "AMDGPU.h"
 #include "GCNSubtarget.h"
 #include "llvm/ADT/SmallSet.h"
@@ -23,13 +24,13 @@ using namespace llvm;
 
 namespace {
 
-class SIPostRABundler : public MachineFunctionPass {
+class SIPostRABundlerLegacy : public MachineFunctionPass {
 public:
   static char ID;
 
 public:
-  SIPostRABundler() : MachineFunctionPass(ID) {
-    initializeSIPostRABundlerPass(*PassRegistry::getPassRegistry());
+  SIPostRABundlerLegacy() : MachineFunctionPass(ID) {
+    initializeSIPostRABundlerLegacyPass(*PassRegistry::getPassRegistry());
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
@@ -42,6 +43,11 @@ class SIPostRABundler : public MachineFunctionPass {
     AU.setPreservesAll();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
+};
+
+class SIPostRABundler {
+public:
+  bool run(MachineFunction &MF);
 
 private:
   const SIRegisterInfo *TRI;
@@ -62,14 +68,15 @@ constexpr uint64_t MemFlags = SIInstrFlags::MTBUF | SIInstrFlags::MUBUF |
 
 } // End anonymous namespace.
 
-INITIALIZE_PASS(SIPostRABundler, DEBUG_TYPE, "SI post-RA bundler", false, false)
+INITIALIZE_PASS(SIPostRABundlerLegacy, DEBUG_TYPE, "SI post-RA bundler", false,
+                false)
 
-char SIPostRABundler::ID = 0;
+char SIPostRABundlerLegacy::ID = 0;
 
-char &llvm::SIPostRABundlerID = SIPostRABundler::ID;
+char &llvm::SIPostRABundlerLegacyID = SIPostRABundlerLegacy::ID;
 
 FunctionPass *llvm::createSIPostRABundlerPass() {
-  return new SIPostRABundler();
+  return new SIPostRABundlerLegacy();
 }
 
 bool SIPostRABundler::isDependentLoad(const MachineInstr &MI) const {
@@ -121,9 +128,19 @@ bool SIPostRABundler::canBundle(const MachineInstr &MI,
           !isDependentLoad(NextMI));
 }
 
-bool SIPostRABundler::runOnMachineFunction(MachineFunction &MF) {
+bool SIPostRABundlerLegacy::runOnMachineFunction(MachineFunction &MF) {
   if (skipFunction(MF.getFunction()))
     return false;
+  return SIPostRABundler().run(MF);
+}
+
+PreservedAnalyses SIPostRABundlerPass::run(MachineFunction &MF,
+                                           MachineFunctionAnalysisManager &) {
+  SIPostRABundler().run(MF);
+  return PreservedAnalyses::all();
+}
+
+bool SIPostRABundler::run(MachineFunction &MF) {
 
   TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
   BitVector BundleUsedRegUnits(TRI->getNumRegUnits());

llvm/lib/Target/AMDGPU/SIPostRABundler.h

@@ -0,0 +1,22 @@
+//===- SIPostRABundler.h ----------------------------------------*- C++- *-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_SIPOSTRABUNDLER_H
+#define LLVM_LIB_TARGET_AMDGPU_SIPOSTRABUNDLER_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+class SIPostRABundlerPass : public PassInfoMixin<SIPostRABundlerPass> {
+public:
+  PreservedAnalyses run(MachineFunction &MF,
+                        MachineFunctionAnalysisManager &MFAM);
+};
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_AMDGPU_SIPOSTRABUNDLER_H

llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir

@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-post-ra-bundler %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=si-post-ra-bundler %s -o - | FileCheck -check-prefix=GCN %s
 
 ---
 name:            bundle_memops