[AMDGPU] Update AMDGPUUsage.rst to document two intrinsics

[jwanggit86]

The AMDGPUUsage.rst file is updated to document tow intrinsics: llvm.amdgcn.mov.dpp and llvm.amdgcn.update.dpp.

[llvmbot]

@llvm/pr-subscribers-llvm-ir

@llvm/pr-subscribers-backend-amdgpu

Author: Jun Wang (jwanggit86)

Changes

The AMDGPUUsage.rst file is updated to document tow intrinsics: llvm.amdgcn.move.dpp and llvm.amdgcn.update.dpp.

---

Full diff: https://github.com/llvm/llvm-project/pull/123816.diff

1 Files Affected:

• (modified) llvm/docs/AMDGPUUsage.rst (+12)

diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 40b393224f15dd..132a7444805620 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -1422,6 +1422,18 @@ The AMDGPU backend implements the following LLVM IR intrinsics.
                                                    Returns a pair for the swapped registers. The first element of the return
                                                    corresponds to the swapped element of the first argument.
 
+  llvm.amdgcn.mov.dpp                              The llvm.amdgcn.mov.dpp.i32 intrinsic represents the mov.dpp operation in AMDGPU.
+                                                   This operation is being deprecated and can be replaced with llvm.amdgcn.update.dpp.
+
+  llvm.amdgcn.update.dpp                           The llvm.amdgcn.update.dpp intrinsic represents the update.dpp operation in AMDGPU.
+                                                   It takes an old value, a source operand, a DPP control operand, a row mask, a bank mask, and a bound control.
+                                                   This operation is equivalent to a sequence of v_mov_b32 operations.
+                                                   It is preferred over llvm.amdgcn.mov.dpp.i32 for future use.
+                                                   `llvm.amdgcn.update.dpp.i32 <old> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>`
+                                                   Should be equivalent to:
+                                                   - `v_mov_b32 <dest> <old>`
+                                                   - `v_mov_b32 <dest> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>`
+
   ==============================================   ==========================================================
 
 .. TODO::

[arsenm]

This is misleading, it's not a mere v_mov_b32.

[jayfoad]

Looks like this was copied directly from the comments in IntrinsicsAMDGPU.td so fixes to the description should go there first (or as well).

[jwanggit86]

Yes, it was copied from the .td file. @arsenm How should this be changed?

[arsenm]

Should mention it's v_mov_b32 with DPP, and mention the types it supports. It's not just i32 anymore

[jayfoad]

Just remove this line? It already says below exactly what v_mov_b32 instructions it is equivalent to.

[jwanggit86]

Added a line to mention supported data types. Previously missed ".i32" suffix has been changed to ".".

[jwanggit86]

Will update the .td file correspondingly once this file is done.