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Merged
wangleiat merged 7 commits into from
Feb 21, 2025
Merged

[lldb][LoongArch] Complete register alias name in AugmentRegisterInfo #124059

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f477770
[𝘀𝗽𝗿] initial version
wangleiat Jan 23, 2025
ba95342
use llvm::StringMap
wangleiat Jan 24, 2025
d03f4f2
add test
wangleiat Feb 5, 2025
4243a81
rebase and add test
wangleiat Feb 6, 2025
b77caf2
add test
wangleiat Feb 20, 2025
d3c8c7c
Address @DavidSpickett's comment
wangleiat Feb 21, 2025
8ad3d66
rebase and resolve conflicts
wangleiat Feb 21, 2025
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42 changes: 17 additions & 25 deletions lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,7 @@
#include <limits>
#include <sstream>

#include "llvm/ADT/StringRef.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/Support/MathExtras.h"

Expand Down Expand Up @@ -644,34 +645,25 @@ void ABISysV_loongarch::AugmentRegisterInfo(
std::vector<lldb_private::DynamicRegisterInfo::Register> &regs) {
lldb_private::RegInfoBasedABI::AugmentRegisterInfo(regs);

static const llvm::StringMap<llvm::StringRef> isa_to_abi_alias_map = {
{"r0", "zero"}, {"r1", "ra"}, {"r2", "tp"}, {"r3", "sp"},
{"r4", "a0"}, {"r5", "a1"}, {"r6", "a2"}, {"r7", "a3"},
{"r8", "a4"}, {"r9", "a5"}, {"r10", "a6"}, {"r11", "a7"},
{"r12", "t0"}, {"r13", "t1"}, {"r14", "t2"}, {"r15", "t3"},
{"r16", "t4"}, {"r17", "t5"}, {"r18", "t6"}, {"r19", "t7"},
{"r20", "t8"}, {"r22", "fp"}, {"r23", "s0"}, {"r24", "s1"},
{"r25", "s2"}, {"r26", "s3"}, {"r27", "s4"}, {"r28", "s5"},
{"r29", "s6"}, {"r30", "s7"}, {"r31", "s8"}};

for (auto it : llvm::enumerate(regs)) {
llvm::StringRef reg_name = it.value().name.GetStringRef();

// Set alt name for certain registers for convenience
if (it.value().name == "r0")
it.value().alt_name.SetCString("zero");
else if (it.value().name == "r1")
it.value().alt_name.SetCString("ra");
else if (it.value().name == "r3")
it.value().alt_name.SetCString("sp");
else if (it.value().name == "r22")
it.value().alt_name.SetCString("fp");
else if (it.value().name == "r4")
it.value().alt_name.SetCString("a0");
else if (it.value().name == "r5")
it.value().alt_name.SetCString("a1");
else if (it.value().name == "r6")
it.value().alt_name.SetCString("a2");
else if (it.value().name == "r7")
it.value().alt_name.SetCString("a3");
else if (it.value().name == "r8")
it.value().alt_name.SetCString("a4");
else if (it.value().name == "r9")
it.value().alt_name.SetCString("a5");
else if (it.value().name == "r10")
it.value().alt_name.SetCString("a6");
else if (it.value().name == "r11")
it.value().alt_name.SetCString("a7");
llvm::StringRef alias_name = isa_to_abi_alias_map.lookup(reg_name);
if (!alias_name.empty())
it.value().alt_name.SetString(alias_name);

// Set generic regnum so lldb knows what the PC, etc is
it.value().regnum_generic = GetGenericNum(it.value().name.GetStringRef());
it.value().regnum_generic = GetGenericNum(reg_name);
}
}
79 changes: 43 additions & 36 deletions lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
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Original file line number Diff line number Diff line change
Expand Up @@ -852,41 +852,42 @@ def test_loongarch64_regs(self):
self.assertTrue(target, VALID_TARGET)
process = target.LoadCore("linux-loongarch64.core")

values = {}
values["r0"] = "0x0000000000000000"
values["r1"] = "0x000000012000016c"
values["r2"] = "0x0000000000000000"
values["r3"] = "0x00007ffffb8249e0"
values["r4"] = "0x0000000000000000"
values["r5"] = "0x000000012000010c"
values["r6"] = "0x0000000000000000"
values["r7"] = "0x0000000000000000"
values["r8"] = "0x0000000000000000"
values["r9"] = "0x0000000000000000"
values["r10"] = "0x0000000000000000"
values["r11"] = "0x00000000000000dd"
values["r12"] = "0x0000000000000000"
values["r13"] = "0x000000000000002f"
values["r14"] = "0x0000000000000000"
values["r15"] = "0x0000000000000000"
values["r16"] = "0x0000000000000000"
values["r17"] = "0x0000000000000000"
values["r18"] = "0x0000000000000000"
values["r19"] = "0x0000000000000000"
values["r20"] = "0x0000000000000000"
values["r21"] = "0x0000000000000000"
values["r22"] = "0x00007ffffb824a10"
values["r23"] = "0x0000000000000000"
values["r24"] = "0x0000000000000000"
values["r25"] = "0x0000000000000000"
values["r26"] = "0x0000000000000000"
values["r27"] = "0x0000000000000000"
values["r28"] = "0x0000000000000000"
values["r29"] = "0x0000000000000000"
values["r30"] = "0x0000000000000000"
values["r31"] = "0x0000000000000000"
values["orig_a0"] = "0x0000555556b62d50"
values["pc"] = "0x000000012000012c"
values = {
"r0": ("0x0000000000000000", "zero"),
"r1": ("0x000000012000016c", "ra"),
"r2": ("0x0000000000000000", "tp"),
"r3": ("0x00007ffffb8249e0", "sp"),
"r4": ("0x0000000000000000", "a0"),
"r5": ("0x000000012000010c", "a1"),
"r6": ("0x0000000000000000", "a2"),
"r7": ("0x0000000000000000", "a3"),
"r8": ("0x0000000000000000", "a4"),
"r9": ("0x0000000000000000", "a5"),
"r10": ("0x0000000000000000", "a6"),
"r11": ("0x00000000000000dd", "a7"),
"r12": ("0x0000000000000000", "t0"),
"r13": ("0x000000000000002f", "t1"),
"r14": ("0x0000000000000000", "t2"),
"r15": ("0x0000000000000000", "t3"),
"r16": ("0x0000000000000000", "t4"),
"r17": ("0x0000000000000000", "t5"),
"r18": ("0x0000000000000000", "t6"),
"r19": ("0x0000000000000000", "t7"),
"r20": ("0x0000000000000000", "t8"),
"r21": ("0x0000000000000000", None),
"r22": ("0x00007ffffb824a10", "fp"),
"r23": ("0x0000000000000000", "s0"),
"r24": ("0x0000000000000000", "s1"),
"r25": ("0x0000000000000000", "s2"),
"r26": ("0x0000000000000000", "s3"),
"r27": ("0x0000000000000000", "s4"),
"r28": ("0x0000000000000000", "s5"),
"r29": ("0x0000000000000000", "s6"),
"r30": ("0x0000000000000000", "s7"),
"r31": ("0x0000000000000000", "s8"),
"orig_a0": ("0x0000555556b62d50", None),
"pc": ("0x000000012000012c", None),
}

fpr_values = {}
fpr_values["f0"] = "0x00000000ffffff05"
Expand Down Expand Up @@ -931,11 +932,17 @@ def test_loongarch64_regs(self):
fpr_values["fcc7"] = "0x01"
fpr_values["fcsr"] = "0x00000000"

for regname, value in values.items():
for regname in values:
value, alias = values[regname]
self.expect(
"register read {}".format(regname),
substrs=["{} = {}".format(regname, value)],
)
if alias:
self.expect(
"register read {}".format(alias),
substrs=["{} = {}".format(regname, value)],
)

for regname, value in fpr_values.items():
self.expect(
Expand Down
35 changes: 35 additions & 0 deletions lldb/test/Shell/Register/Inputs/loongarch64-gp-read.cpp
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@@ -0,0 +1,35 @@
int main() {
asm volatile("li.w $r1, 1\n\t"
"li.w $r2, 2\n\t"
"li.w $r3, 3\n\t"
"li.w $r4, 4\n\t"
"li.w $r5, 5\n\t"
"li.w $r6, 6\n\t"
"li.w $r7, 7\n\t"
"li.w $r8, 8\n\t"
"li.w $r9, 9\n\t"
"li.w $r10, 10\n\t"
"li.w $r11, 11\n\t"
"li.w $r12, 12\n\t"
"li.w $r13, 13\n\t"
"li.w $r14, 14\n\t"
"li.w $r15, 15\n\t"
"li.w $r16, 16\n\t"
"li.w $r17, 17\n\t"
"li.w $r18, 18\n\t"
"li.w $r19, 19\n\t"
"li.w $r20, 20\n\t"
"li.w $r21, 21\n\t"
"li.w $r22, 22\n\t"
"li.w $r23, 23\n\t"
"li.w $r24, 24\n\t"
"li.w $r25, 25\n\t"
"li.w $r26, 26\n\t"
"li.w $r27, 27\n\t"
"li.w $r28, 28\n\t"
"li.w $r29, 29\n\t"
"li.w $r30, 30\n\t"
"li.w $r31, 31\n\t"
"break 5\n\t");
return 0;
}
39 changes: 39 additions & 0 deletions lldb/test/Shell/Register/loongarch64-gp-read.test
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Original file line number Diff line number Diff line change
@@ -0,0 +1,39 @@
# REQUIRES: native && target-loongarch64
# RUN: %clangxx_host %p/Inputs/loongarch64-gp-read.cpp -o %t
# RUN: %lldb -b -s %s %t | FileCheck %s
process launch

## read alias name
register read zero ra tp sp a0 a1 a2 a3 a4 a5 a6 a7 t0 t1 t2 t3 t4 t5 t6 t7 t8 r21 fp s0 s1 s2 s3 s4 s5 s6 s7 s8
# CHECK-DAG: r0 = 0x0000000000000000
# CHECK-DAG: r1 = 0x0000000000000001
# CHECK-DAG: r2 = 0x0000000000000002
# CHECK-DAG: r3 = 0x0000000000000003
# CHECK-DAG: r4 = 0x0000000000000004
# CHECK-DAG: r5 = 0x0000000000000005
# CHECK-DAG: r6 = 0x0000000000000006
# CHECK-DAG: r7 = 0x0000000000000007
# CHECK-DAG: r8 = 0x0000000000000008
# CHECK-DAG: r9 = 0x0000000000000009
# CHECK-DAG: r10 = 0x000000000000000a
# CHECK-DAG: r11 = 0x000000000000000b
# CHECK-DAG: r12 = 0x000000000000000c
# CHECK-DAG: r13 = 0x000000000000000d
# CHECK-DAG: r14 = 0x000000000000000e
# CHECK-DAG: r15 = 0x000000000000000f
# CHECK-DAG: r16 = 0x0000000000000010
# CHECK-DAG: r17 = 0x0000000000000011
# CHECK-DAG: r18 = 0x0000000000000012
# CHECK-DAG: r19 = 0x0000000000000013
# CHECK-DAG: r20 = 0x0000000000000014
# CHECK-DAG: r21 = 0x0000000000000015
# CHECK-DAG: r22 = 0x0000000000000016
# CHECK-DAG: r23 = 0x0000000000000017
# CHECK-DAG: r24 = 0x0000000000000018
# CHECK-DAG: r25 = 0x0000000000000019
# CHECK-DAG: r26 = 0x000000000000001a
# CHECK-DAG: r27 = 0x000000000000001b
# CHECK-DAG: r28 = 0x000000000000001c
# CHECK-DAG: r29 = 0x000000000000001d
# CHECK-DAG: r30 = 0x000000000000001e
# CHECK-DAG: r31 = 0x000000000000001f
2 changes: 2 additions & 0 deletions llvm/utils/lit/lit/llvm/config.py
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Original file line number Diff line number Diff line change
Expand Up @@ -169,6 +169,8 @@ def __init__(self, lit_config, config):
features.add("target-aarch64")
elif re.match(r"^arm.*", target_triple):
features.add("target-arm")
elif re.match(r"^loongarch64.*", target_triple):
features.add("target-loongarch64")
if re.match(r'^ppc64le.*-linux', target_triple):
features.add('target=powerpc64le-linux')

Expand Down