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[lldb][RISC-V] Extended if conditions to support alias names for registers #124475

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Merged
DavidSpickett merged 1 commit into from
Feb 20, 2025
Merged

[lldb][RISC-V] Extended if conditions to support alias names for registers #124475

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54 changes: 54 additions & 0 deletions lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -850,8 +850,62 @@ void ABISysV_riscv::AugmentRegisterInfo(
it.value().alt_name.SetCString("x3");
else if (it.value().name == "fp")
it.value().alt_name.SetCString("s0");
else if (it.value().name == "tp")
it.value().alt_name.SetCString("x4");
else if (it.value().name == "s0")
it.value().alt_name.SetCString("x8");
else if (it.value().name == "s1")
it.value().alt_name.SetCString("x9");
else if (it.value().name == "t0")
it.value().alt_name.SetCString("x5");
else if (it.value().name == "t1")
it.value().alt_name.SetCString("x6");
else if (it.value().name == "t2")
it.value().alt_name.SetCString("x7");
else if (it.value().name == "a0")
it.value().alt_name.SetCString("x10");
else if (it.value().name == "a1")
it.value().alt_name.SetCString("x11");
else if (it.value().name == "a2")
it.value().alt_name.SetCString("x12");
else if (it.value().name == "a3")
it.value().alt_name.SetCString("x13");
else if (it.value().name == "a4")
it.value().alt_name.SetCString("x14");
else if (it.value().name == "a5")
it.value().alt_name.SetCString("x15");
else if (it.value().name == "a6")
it.value().alt_name.SetCString("x16");
else if (it.value().name == "a7")
it.value().alt_name.SetCString("x17");
else if (it.value().name == "s2")
it.value().alt_name.SetCString("x18");
else if (it.value().name == "s3")
it.value().alt_name.SetCString("x19");
else if (it.value().name == "s4")
it.value().alt_name.SetCString("x20");
else if (it.value().name == "s5")
it.value().alt_name.SetCString("x21");
else if (it.value().name == "s6")
it.value().alt_name.SetCString("x22");
else if (it.value().name == "s7")
it.value().alt_name.SetCString("x23");
else if (it.value().name == "s8")
it.value().alt_name.SetCString("x24");
else if (it.value().name == "s9")
it.value().alt_name.SetCString("x25");
else if (it.value().name == "s10")
it.value().alt_name.SetCString("x26");
else if (it.value().name == "s11")
it.value().alt_name.SetCString("x27");
else if (it.value().name == "t3")
it.value().alt_name.SetCString("x28");
else if (it.value().name == "t4")
it.value().alt_name.SetCString("x29");
else if (it.value().name == "t5")
it.value().alt_name.SetCString("x30");
else if (it.value().name == "t6")
it.value().alt_name.SetCString("x31");

// Set generic regnum so lldb knows what the PC, etc is
it.value().regnum_generic = GetGenericNum(it.value().name.GetStringRef());
Expand Down
148 changes: 148 additions & 0 deletions lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
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Original file line number Diff line number Diff line change
Expand Up @@ -652,6 +652,154 @@ def haltReason(self):
)
self.match("register read s31", ["s31 = 128"])

@skipIfXmlSupportMissing
@skipIfRemote
@skipIfLLVMTargetMissing("RISCV")
def test_riscv64_regs(self):
"""Test grabbing various riscv64 registers from gdbserver."""

class MyResponder(MockGDBServerResponder):
reg_data = (
"0102030405060708" # zero
"0102030405060708" # ra
"0102030405060708" # sp
"0102030405060708" # gp
"0102030405060708" # tp
"0102030405060708" # t0
"0102030405060708" # t1
"0102030405060708" # t2
"0102030405060708" # fp
"0102030405060708" # s1
"0102030405060708" # a0
"0102030405060708" # a1
"0102030405060708" # a2
"0102030405060708" # a3
"0102030405060708" # a4
"0102030405060708" # a5
"0102030405060708" # a6
"0102030405060708" # a7
"0102030405060708" # s2
"0102030405060708" # s3
"0102030405060708" # s4
"0102030405060708" # s5
"0102030405060708" # s6
"0102030405060708" # s7
"0102030405060708" # s8
"0102030405060708" # s9
"0102030405060708" # s10
"0102030405060708" # s11
"0102030405060708" # t3
"0102030405060708" # t4
"0102030405060708" # t5
"0102030405060708" # t6
)

def qXferRead(self, obj, annex, offset, length):
if annex == "target.xml":
# Note that this XML does not include any aliases, LLDB must generate them itself.
return (
"""<?xml version="1.0"?>
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<target>
<architecture>riscv</architecture>
<feature name="org.gnu.gdb.riscv.cpu">
<reg name="zero" bitsize="64" type="int"/>
<reg name="ra" bitsize="64" type="code_ptr"/>
<reg name="sp" bitsize="64" type="data_ptr"/>
<reg name="gp" bitsize="64" type="data_ptr"/>
<reg name="tp" bitsize="64" type="data_ptr"/>
<reg name="t0" bitsize="64" type="int"/>
<reg name="t1" bitsize="64" type="int"/>
<reg name="t2" bitsize="64" type="int"/>
<reg name="fp" bitsize="64" type="data_ptr"/>
<reg name="s1" bitsize="64" type="int"/>
<reg name="a0" bitsize="64" type="int"/>
<reg name="a1" bitsize="64" type="int"/>
<reg name="a2" bitsize="64" type="int"/>
<reg name="a3" bitsize="64" type="int"/>
<reg name="a4" bitsize="64" type="int"/>
<reg name="a5" bitsize="64" type="int"/>
<reg name="a6" bitsize="64" type="int"/>
<reg name="a7" bitsize="64" type="int"/>
<reg name="s2" bitsize="64" type="int"/>
<reg name="s3" bitsize="64" type="int"/>
<reg name="s4" bitsize="64" type="int"/>
<reg name="s5" bitsize="64" type="int"/>
<reg name="s6" bitsize="64" type="int"/>
<reg name="s7" bitsize="64" type="int"/>
<reg name="s8" bitsize="64" type="int"/>
<reg name="s9" bitsize="64" type="int"/>
<reg name="s10" bitsize="64" type="int"/>
<reg name="s11" bitsize="64" type="int"/>
<reg name="t3" bitsize="64" type="int"/>
<reg name="t4" bitsize="64" type="int"/>
<reg name="t5" bitsize="64" type="int"/>
<reg name="t6" bitsize="64" type="int"/>
<reg name="pc" bitsize="64" type="code_ptr"/>
</feature>
</target>""",
False,
)
else:
return None, False

def readRegister(self, regnum):
return ""

def readRegisters(self):
return self.reg_data

def writeRegisters(self, reg_hex):
self.reg_data = reg_hex
return "OK"

def haltReason(self):
return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;"

self.server.responder = MyResponder()

target = self.createTarget("basic_eh_frame-riscv64.yaml")
process = self.connect(target)
lldbutil.expect_state_changes(
self, self.dbg.GetListener(), process, [lldb.eStateStopped]
)

# test generic aliases
self.match("register read x0", ["zero = 0x0807060504030201"])
self.match("register read x1", ["ra = 0x0807060504030201"])
self.match("register read x2", ["sp = 0x0807060504030201"])
self.match("register read x3", ["gp = 0x0807060504030201"])
self.match("register read x4", ["tp = 0x0807060504030201"])
self.match("register read x5", ["t0 = 0x0807060504030201"])
self.match("register read x6", ["t1 = 0x0807060504030201"])
self.match("register read x7", ["t2 = 0x0807060504030201"])
# Register x8 is probably not working because it has two aliases fp, s0
# See issue #127900
# self.match("register read x8", ["fp = 0x0807060504030201"])
self.match("register read x9", ["s1 = 0x0807060504030201"])
self.match("register read x10", ["a0 = 0x0807060504030201"])
self.match("register read x11", ["a1 = 0x0807060504030201"])
self.match("register read x12", ["a2 = 0x0807060504030201"])
self.match("register read x13", ["a3 = 0x0807060504030201"])
self.match("register read x14", ["a4 = 0x0807060504030201"])
self.match("register read x15", ["a5 = 0x0807060504030201"])
self.match("register read x16", ["a6 = 0x0807060504030201"])
self.match("register read x17", ["a7 = 0x0807060504030201"])
self.match("register read x18", ["s2 = 0x0807060504030201"])
self.match("register read x19", ["s3 = 0x0807060504030201"])
self.match("register read x20", ["s4 = 0x0807060504030201"])
self.match("register read x21", ["s5 = 0x0807060504030201"])
self.match("register read x22", ["s6 = 0x0807060504030201"])
self.match("register read x23", ["s7 = 0x0807060504030201"])
self.match("register read x24", ["s8 = 0x0807060504030201"])
self.match("register read x25", ["s9 = 0x0807060504030201"])
self.match("register read x26", ["s10 = 0x0807060504030201"])
self.match("register read x27", ["s11 = 0x0807060504030201"])
self.match("register read x28", ["t3 = 0x0807060504030201"])
self.match("register read x29", ["t4 = 0x0807060504030201"])
self.match("register read x30", ["t5 = 0x0807060504030201"])
self.match("register read x31", ["t6 = 0x0807060504030201"])

@skipIfXmlSupportMissing
@skipIfRemote
@skipIfLLVMTargetMissing("X86")
Expand Down
20 changes: 20 additions & 0 deletions lldb/test/API/functionalities/gdb_remote_client/basic_eh_frame-riscv64.yaml
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Original file line number Diff line number Diff line change
@@ -0,0 +1,20 @@
--- !ELF
FileHeader:
Class: ELFCLASS64
Data: ELFDATA2LSB
Type: ET_EXEC
Machine: EM_RISCV
Sections:
- Name: .text
Type: SHT_PROGBITS
Flags: [ SHF_ALLOC, SHF_EXECINSTR ]
Address: 0x0000000000000570
AddressAlign: 0x0000000000000004
Content: DEADBEEF
- Name: .eh_frame
Type: SHT_PROGBITS
Flags: [ SHF_ALLOC ]
Address: 0x0000000000000688
AddressAlign: 0x0000000000000008
Content: 000006881000000000000000037a5200017c0101000006981b0d02001000000018000000ccfeffff000006a82200000000070100200000002c000000000006b89cffffff1000000000420e1042880242000006c80c080046c80c0210420e000000000000
...
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