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Reapply "[AArch64] Combine and and lsl into ubfiz" (#123356) #124576

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Merged
c-rhodes merged 3 commits into from
Jan 28, 2025
Merged

Reapply "[AArch64] Combine and and lsl into ubfiz" (#123356) #124576

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9f292d7
Reapply "[AArch64] Combine and and lsl into ubfiz" (#123356)
c-rhodes Jan 20, 2025
4835941
fix
c-rhodes Jan 27, 2025
3df21b6
address comments
c-rhodes Jan 27, 2025
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9 changes: 8 additions & 1 deletion llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -26372,8 +26372,15 @@ static SDValue performSHLCombine(SDNode *N,

SDLoc DL(N);
EVT VT = N->getValueType(0);
SDValue X = Op0->getOperand(0);

// Don't combine unless (shl C1, C2) can be constant folded. Otherwise,
// DAGCombiner will simplify (and (op x...), (op y...)) -> (op (and x, y))
// causing infinite loop. Result may also be worse.
SDValue NewRHS = DAG.getNode(ISD::SHL, DL, VT, C1, C2);
if (!isa<ConstantSDNode>(NewRHS))
return SDValue();

SDValue X = Op0->getOperand(0);
SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, X, C2);
return DAG.getNode(ISD::AND, DL, VT, NewShift, NewRHS);
}
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17 changes: 17 additions & 0 deletions llvm/test/CodeGen/AArch64/xbfiz.ll
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Expand Up @@ -85,3 +85,20 @@ define i64 @lsl_zext_i16_i64(i16 %b) {
%2 = shl i64 %1, 1
ret i64 %2
}

; Regression test for:
; https://github.com/llvm/llvm-project/pull/118974#issuecomment-2598521878
; that exposed infinite loop in DAGCombiner.
define void @_f(ptr %0, ptr %1, i64 %2) {
; CHECK-LABEL: @_f
store i64 -2401053089408754003, ptr %1, align 8
%4 = and i64 %2, -2401053089408754003
%5 = shl i64 %4, 1
store i64 %5, ptr %0, align 1
%6 = lshr i64 %4, 54
%7 = shl i64 %2, 10
%8 = and i64 %7, 131072
%9 = or i64 %8, %6
store i64 %9, ptr %1, align 1
ret void
}
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