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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -56,7 +56,7 @@ AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,

Register Base;
if (KnownBits && mi_match(Reg, MRI, m_GOr(m_Reg(Base), m_ICst(Offset))) &&
KnownBits->maskedValueIsZero(Base, APInt(32, Offset)))
KnownBits->maskedValueIsZero(Base, APInt(32, Offset, /*isSigned=*/true)))
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APSint?

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@dfukalov dfukalov Jan 28, 2025

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Jay suggested to use APInt in the same case #122251 (comment)

@jayfoad?

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What is the suggestion? I don't even see how you could use APSInt here.

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Oh, indeed, that was just an incorrect usage of APSInt(BitWidth, isUnsigned)...

return std::pair(Base, Offset);

// Handle G_PTRTOINT (G_PTR_ADD base, const) case
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14 changes: 14 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/assert-signed-apint.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
; REQUIRES: asserts
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Does not require asserts

; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -stop-after=instruction-select -o - %s | FileCheck %s
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Don't need -verify-machineinstrs


; Check that APInt doesn't assert on creation from -2147483648 value.

; CHECK-LABEL: @test
; CHECK: S_BUFFER_LOAD_DWORD_SGPR_IMM
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use update_mir_test_checks


define amdgpu_cs void @test(<4 x i32> inreg %base, i32 inreg %i, ptr addrspace(1) inreg %out) {
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Maybe just add this case to an existing file that tests buffer offsets?

%off = or i32 %i, -2147483648
%v = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %base, i32 %off, i32 0)
store i32 %v, ptr addrspace(1) %out, align 4
ret void
}
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