[AMDGPU][NewPM] Port GCNNSAReassign pass to new pass manager #125034
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
arsenm
approved these changes
Jan 30, 2025
Member
|
@llvm/pr-subscribers-backend-amdgpu Author: Vikram Hegde (vikramRH) Changesdraft for now since validation requires greedy regalloc and virtregrewrite to be ported first. Full diff: https://github.com/llvm/llvm-project/pull/125034.diff 6 Files Affected:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 3d5a44a3623a00..734b0699e6f772 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -448,8 +448,8 @@ ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringLegacyPass();
void initializeAMDGPUOpenCLEnqueuedBlockLoweringLegacyPass(PassRegistry &);
extern char &AMDGPUOpenCLEnqueuedBlockLoweringLegacyID;
-void initializeGCNNSAReassignPass(PassRegistry &);
-extern char &GCNNSAReassignID;
+void initializeGCNNSAReassignLegacyPass(PassRegistry &);
+extern char &GCNNSAReassignLegacyID;
void initializeGCNPreRALongBranchRegPass(PassRegistry &);
extern char &GCNPreRALongBranchRegID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index 45e2f0d9097adf..07e45c6133c4de 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -97,6 +97,7 @@ FUNCTION_PASS_WITH_PARAMS(
#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS)
#endif
MACHINE_FUNCTION_PASS("amdgpu-isel", AMDGPUISelDAGToDAGPass(*this))
+MACHINE_FUNCTION_PASS("amdgpu-nsa-reassign", GCNNSAReassignPass())
MACHINE_FUNCTION_PASS("gcn-dpp-combine", GCNDPPCombinePass())
MACHINE_FUNCTION_PASS("si-fix-sgpr-copies", SIFixSGPRCopiesPass())
MACHINE_FUNCTION_PASS("si-fix-vgpr-copies", SIFixVGPRCopiesPass())
@@ -115,7 +116,6 @@ MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
#define DUMMY_MACHINE_FUNCTION_PASS(NAME, CREATE_PASS)
DUMMY_MACHINE_FUNCTION_PASS("amdgpu-insert-delay-alu", AMDGPUInsertDelayAluPass())
-DUMMY_MACHINE_FUNCTION_PASS("amdgpu-nsa-reassign", GCNNSAReassignPass())
DUMMY_MACHINE_FUNCTION_PASS("amdgpu-pre-ra-long-branch-reg", GCNPreRALongBranchRegPass())
DUMMY_MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations", GCNPreRAOptimizationsPass())
DUMMY_MACHINE_FUNCTION_PASS("amdgpu-rewrite-partial-reg-uses", GCNRewritePartialRegUsesPass())
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 1f29589146c803..5e27584459df24 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -31,6 +31,7 @@
#include "AMDGPUUnifyDivergentExitNodes.h"
#include "GCNDPPCombine.h"
#include "GCNIterativeScheduler.h"
+#include "GCNNSAReassign.h"
#include "GCNSchedStrategy.h"
#include "GCNVOPDUtils.h"
#include "R600.h"
@@ -542,7 +543,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
initializeAMDGPUImageIntrinsicOptimizerPass(*PR);
initializeAMDGPUPrintfRuntimeBindingPass(*PR);
initializeAMDGPUResourceUsageAnalysisPass(*PR);
- initializeGCNNSAReassignPass(*PR);
+ initializeGCNNSAReassignLegacyPass(*PR);
initializeGCNPreRAOptimizationsPass(*PR);
initializeGCNPreRALongBranchRegPass(*PR);
initializeGCNRewritePartialRegUsesPass(*PR);
@@ -1508,7 +1509,7 @@ void GCNPassConfig::addOptimizedRegAlloc() {
bool GCNPassConfig::addPreRewrite() {
if (EnableRegReassign)
- addPass(&GCNNSAReassignID);
+ addPass(&GCNNSAReassignLegacyID);
return true;
}
@@ -2091,6 +2092,12 @@ Error AMDGPUCodeGenPassBuilder::addInstSelector(AddMachinePass &addPass) const {
return Error::success();
}
+void AMDGPUCodeGenPassBuilder::addPreRewrite(AddMachinePass &addPass) const {
+ if (EnableRegReassign) {
+ addPass(GCNNSAReassignPass());
+ }
+}
+
void AMDGPUCodeGenPassBuilder::addMachineSSAOptimization(
AddMachinePass &addPass) const {
Base::addMachineSSAOptimization(addPass);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index 24b4da3a68f67e..89ee210a2cd280 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -175,6 +175,7 @@ class AMDGPUCodeGenPassBuilder
void addILPOpts(AddMachinePass &) const;
void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const;
Error addInstSelector(AddMachinePass &) const;
+ void addPreRewrite(AddMachinePass &) const;
void addMachineSSAOptimization(AddMachinePass &) const;
void addPostRegAlloc(AddMachinePass &) const;
diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
index 85e79aa4b7595e..85e7c948f3d53d 100644
--- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
@@ -13,6 +13,7 @@
///
//===----------------------------------------------------------------------===//
+#include "GCNNSAReassign.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "SIMachineFunctionInfo.h"
@@ -34,26 +35,12 @@ STATISTIC(NumNSAConverted,
"Number of NSA instructions changed to sequential");
namespace {
-
-class GCNNSAReassign : public MachineFunctionPass {
+class GCNNSAReassignImpl {
public:
- static char ID;
-
- GCNNSAReassign() : MachineFunctionPass(ID) {
- initializeGCNNSAReassignPass(*PassRegistry::getPassRegistry());
- }
-
- bool runOnMachineFunction(MachineFunction &MF) override;
+ GCNNSAReassignImpl(VirtRegMap *VM, LiveRegMatrix *LM, LiveIntervals *LS)
+ : VRM(VM), LRM(LM), LIS(LS) {}
- StringRef getPassName() const override { return "GCN NSA Reassign"; }
-
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.addRequired<LiveIntervalsWrapperPass>();
- AU.addRequired<VirtRegMapWrapperLegacy>();
- AU.addRequired<LiveRegMatrixWrapperLegacy>();
- AU.setPreservesAll();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
+ bool run(MachineFunction &MF);
private:
using NSA_Status = enum {
@@ -90,24 +77,43 @@ class GCNNSAReassign : public MachineFunctionPass {
bool scavengeRegs(SmallVectorImpl<LiveInterval *> &Intervals) const;
};
+class GCNNSAReassignLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+
+ GCNNSAReassignLegacy() : MachineFunctionPass(ID) {
+ initializeGCNNSAReassignLegacyPass(*PassRegistry::getPassRegistry());
+ }
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+ StringRef getPassName() const override { return "GCN NSA Reassign"; };
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.addRequired<LiveIntervalsWrapperPass>();
+ AU.addRequired<VirtRegMapWrapperLegacy>();
+ AU.addRequired<LiveRegMatrixWrapperLegacy>();
+ AU.setPreservesAll();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+};
+
} // End anonymous namespace.
-INITIALIZE_PASS_BEGIN(GCNNSAReassign, DEBUG_TYPE, "GCN NSA Reassign",
+INITIALIZE_PASS_BEGIN(GCNNSAReassignLegacy, DEBUG_TYPE, "GCN NSA Reassign",
false, false)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(LiveRegMatrixWrapperLegacy)
-INITIALIZE_PASS_END(GCNNSAReassign, DEBUG_TYPE, "GCN NSA Reassign",
- false, false)
-
+INITIALIZE_PASS_END(GCNNSAReassignLegacy, DEBUG_TYPE, "GCN NSA Reassign", false,
+ false)
-char GCNNSAReassign::ID = 0;
+char GCNNSAReassignLegacy::ID = 0;
-char &llvm::GCNNSAReassignID = GCNNSAReassign::ID;
+char &llvm::GCNNSAReassignLegacyID = GCNNSAReassignLegacy::ID;
-bool
-GCNNSAReassign::tryAssignRegisters(SmallVectorImpl<LiveInterval *> &Intervals,
- unsigned StartReg) const {
+bool GCNNSAReassignImpl::tryAssignRegisters(
+ SmallVectorImpl<LiveInterval *> &Intervals, unsigned StartReg) const {
unsigned NumRegs = Intervals.size();
for (unsigned N = 0; N < NumRegs; ++N)
@@ -124,7 +130,7 @@ GCNNSAReassign::tryAssignRegisters(SmallVectorImpl<LiveInterval *> &Intervals,
return true;
}
-bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const {
+bool GCNNSAReassignImpl::canAssign(unsigned StartReg, unsigned NumRegs) const {
for (unsigned N = 0; N < NumRegs; ++N) {
unsigned Reg = StartReg + N;
if (!MRI->isAllocatable(Reg))
@@ -139,8 +145,8 @@ bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const {
return true;
}
-bool
-GCNNSAReassign::scavengeRegs(SmallVectorImpl<LiveInterval *> &Intervals) const {
+bool GCNNSAReassignImpl::scavengeRegs(
+ SmallVectorImpl<LiveInterval *> &Intervals) const {
unsigned NumRegs = Intervals.size();
if (NumRegs > MaxNumVGPRs)
@@ -158,8 +164,8 @@ GCNNSAReassign::scavengeRegs(SmallVectorImpl<LiveInterval *> &Intervals) const {
return false;
}
-GCNNSAReassign::NSA_Status
-GCNNSAReassign::CheckNSA(const MachineInstr &MI, bool Fast) const {
+GCNNSAReassignImpl::NSA_Status
+GCNNSAReassignImpl::CheckNSA(const MachineInstr &MI, bool Fast) const {
const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
if (!Info)
return NSA_Status::NOT_NSA;
@@ -235,16 +241,13 @@ GCNNSAReassign::CheckNSA(const MachineInstr &MI, bool Fast) const {
return NSA ? NSA_Status::NON_CONTIGUOUS : NSA_Status::CONTIGUOUS;
}
-bool GCNNSAReassign::runOnMachineFunction(MachineFunction &MF) {
+bool GCNNSAReassignImpl::run(MachineFunction &MF) {
ST = &MF.getSubtarget<GCNSubtarget>();
if (!ST->hasNSAEncoding() || !ST->hasNonNSAEncoding())
return false;
MRI = &MF.getRegInfo();
TRI = ST->getRegisterInfo();
- VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
- LRM = &getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
- LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
MaxNumVGPRs = ST->getMaxNumVGPRs(MF);
@@ -367,3 +370,24 @@ bool GCNNSAReassign::runOnMachineFunction(MachineFunction &MF) {
return Changed;
}
+
+bool GCNNSAReassignLegacy::runOnMachineFunction(MachineFunction &MF) {
+ auto *VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
+ auto *LRM = &getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
+ auto *LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
+
+ GCNNSAReassignImpl Impl(VRM, LRM, LIS);
+ return Impl.run(MF);
+}
+
+PreservedAnalyses
+GCNNSAReassignPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ auto &VRM = MFAM.getResult<VirtRegMapAnalysis>(MF);
+ auto &LRM = MFAM.getResult<LiveRegMatrixAnalysis>(MF);
+ auto &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF);
+
+ GCNNSAReassignImpl Impl(&VRM, &LRM, &LIS);
+ Impl.run(MF);
+ return PreservedAnalyses::all();
+}
diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h
new file mode 100644
index 00000000000000..08798badd47873
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h
@@ -0,0 +1,22 @@
+//===- GCNNSAReassign.h ---------------------------------------*- C++- *-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_GCNNSAREASSIGN_H
+#define LLVM_LIB_TARGET_AMDGPU_GCNNSAREASSIGN_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+class GCNNSAReassignPass : public PassInfoMixin<GCNNSAReassignPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_AMDGPU_GCNNSAREASSIGN_H
|
arsenm
approved these changes
Jan 31, 2025
vikramRH
force-pushed
the
enable_reassign_npm
branch
from
0164019 to
1aa2a5e
Compare
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
vikramRH
force-pushed
the
enable_reassign_npm
branch
from
1aa2a5e to
c67f18b
Compare
optimisan
approved these changes
Feb 17, 2025
Collaborator
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/134/builds/13592 Here is the relevant piece of the build log for the reference |
Collaborator
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/81/builds/4844 Here is the relevant piece of the build log for the reference |
wldfngrs
pushed a commit
to wldfngrs/llvm-project
that referenced
this pull request
Feb 19, 2025
…5034) tests to be added while porting virtregrewrite and greedy regalloc
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
5 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
tests to be added while porting virtregrewrite and greedy regalloc