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[NFC][TableGen] Code cleanup in CodeGenTarget.cpp #125569

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Merged
merged 1 commit into from
Feb 4, 2025
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[NFC][TableGen] Code cleanup in CodeGenTarget.cpp #125569

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32 changes: 16 additions & 16 deletions llvm/utils/TableGen/Common/CodeGenTarget.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,8 @@
#include <tuple>
using namespace llvm;

cl::OptionCategory AsmParserCat("Options for -gen-asm-parser");
cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer");
static cl::OptionCategory AsmParserCat("Options for -gen-asm-parser");
static cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer");

static cl::opt<unsigned>
AsmParserNum("asmparsernum", cl::init(0),
Expand Down Expand Up @@ -64,9 +64,9 @@ StringRef llvm::getEnumName(MVT::SimpleValueType T) {
std::string llvm::getQualifiedName(const Record *R) {
std::string Namespace;
if (R->getValue("Namespace"))
Namespace = std::string(R->getValueAsString("Namespace"));
Namespace = R->getValueAsString("Namespace").str();
if (Namespace.empty())
return std::string(R->getName());
return R->getName().str();
return Namespace + "::" + R->getName().str();
}

Expand Down Expand Up @@ -166,14 +166,15 @@ CodeGenRegBank &CodeGenTarget::getRegBank() const {
const CodeGenRegisterClass *CodeGenTarget::getSuperRegForSubReg(
const ValueTypeByHwMode &ValueTy, CodeGenRegBank &RegBank,
const CodeGenSubRegIndex *SubIdx, bool MustBeAllocatable) const {
std::vector<CodeGenRegisterClass *> Candidates;
std::vector<const CodeGenRegisterClass *> Candidates;
auto &RegClasses = RegBank.getRegClasses();

// Try to find a register class which supports ValueTy, and also contains
// SubIdx.
for (CodeGenRegisterClass &RC : RegClasses) {
for (const CodeGenRegisterClass &RC : RegClasses) {
// Is there a subclass of this class which contains this subregister index?
CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx);
const CodeGenRegisterClass *SubClassWithSubReg =
RC.getSubClassWithSubReg(SubIdx);
if (!SubClassWithSubReg)
continue;

Expand Down Expand Up @@ -268,32 +269,32 @@ void CodeGenTarget::ReadInstructions() const {
}

static const CodeGenInstruction *GetInstByName(
const char *Name,
StringRef Name,
const DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>> &Insts,
const RecordKeeper &Records) {
const Record *Rec = Records.getDef(Name);

const auto I = Insts.find(Rec);
if (!Rec || I == Insts.end())
PrintFatalError(Twine("Could not find '") + Name + "' instruction!");
PrintFatalError("Could not find '" + Name + "' instruction!");
return I->second.get();
}

static const char *FixedInstrs[] = {
#define HANDLE_TARGET_OPCODE(OPC) #OPC,
#include "llvm/Support/TargetOpcodes.def"
nullptr};
};

unsigned CodeGenTarget::getNumFixedInstructions() {
return std::size(FixedInstrs) - 1;
return std::size(FixedInstrs);
}

/// Return all of the instructions defined by the target, ordered by
/// their enum value.
void CodeGenTarget::ComputeInstrsByEnum() const {
const auto &Insts = getInstructions();
for (const char *const *p = FixedInstrs; *p; ++p) {
const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
for (const char *Name : FixedInstrs) {
const CodeGenInstruction *Instr = GetInstByName(Name, Insts, Records);
assert(Instr && "Missing target independent instruction");
assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
InstrsByEnum.push_back(Instr);
Expand Down Expand Up @@ -324,9 +325,8 @@ void CodeGenTarget::ComputeInstrsByEnum() const {
});

// Assign an enum value to each instruction according to the sorted order.
unsigned Num = 0;
for (const CodeGenInstruction *Inst : InstrsByEnum)
Inst->EnumVal = Num++;
for (const auto &[Idx, Inst] : enumerate(InstrsByEnum))
Inst->EnumVal = Idx;
}

/// isLittleEndianEncoding - Return whether this target encodes its instruction
Expand Down